[PATCH v2 0/3] arm64/cache: Fix cache_type_cwg() for register generation

[PATCH v2 0/3] arm64/cache: Fix cache_type_cwg() for register generation

[Mark Brown]

Ard noticed that in converting CTR_EL0 to automatic generation we broke
cache_type_cwg() since it was using a non-standard way of specifying
_MASK that masks after rather than before shifting to retrieve the
value. We could fix this directly in a single patch but there has been
demand to also convert to use the SYS_FIELD_GET() accessor which
requires a few preparatory patches to make that safe for direct use in
cache.h.

v2:
 - Use SYS_FIELD_GET()

Mark Brown (3):
  arm64/sysreg: Directly include bitfield.h
  arm64/sysreg: Guard SYS_FIELD_ macros for asm
  arm64/cache: Fix cache_type_cwg() for register generation

 arch/arm64/include/asm/cache.h  | 2 +-
 arch/arm64/include/asm/sysreg.h | 5 +++--
 2 files changed, 4 insertions(+), 3 deletions(-)


base-commit: 568035b01cfb107af8d2e4bd2fb9aea22cf5b868
-- 
2.30.2


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[PATCH v2 1/3] arm64/sysreg: Directly include bitfield.h

[Mark Brown]

The SYS_FIELD_ macros in sysreg.h use definitions from bitfield.h but there
is no direct inclusion of it, add one to ensure that sysreg.h is directly
usable.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/asm/sysreg.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 7c71358d44c4..c67002677015 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -1116,6 +1116,7 @@
 
 #else
 
+#include <linux/bitfield.h>
 #include <linux/build_bug.h>
 #include <linux/types.h>
 #include <asm/alternative.h>
-- 
2.30.2


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[PATCH v2 2/3] arm64/sysreg: Guard SYS_FIELD_ macros for asm

[Mark Brown]

The SYS_FIELD_ macros are not safe for assembly contexts, move them inside
the guarded section.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/asm/sysreg.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index c67002677015..818df938a7ad 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -1210,8 +1210,6 @@
 	par;								\
 })
 
-#endif
-
 #define SYS_FIELD_GET(reg, field, val)		\
 		 FIELD_GET(reg##_##field##_MASK, val)
 
@@ -1221,4 +1219,6 @@
 #define SYS_FIELD_PREP_ENUM(reg, field, val)		\
 		 FIELD_PREP(reg##_##field##_MASK, reg##_##field##_##val)
 
+#endif
+
 #endif	/* __ASM_SYSREG_H */
-- 
2.30.2


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[PATCH v2 3/3] arm64/cache: Fix cache_type_cwg() for register generation

[Mark Brown]

Ard noticed that since we converted CTR_EL0 to automatic generation we have
been seeing errors on some systems handling the value of cache_type_cwg()
such as

   CPU features: No Cache Writeback Granule information, assuming 128

This is because the manual definition of CTR_EL0_CWG_MASK was done without
a shift while our convention is to define the mask after shifting. This
means that the user in cache_type_cwg() was broken as it was written for
the manually written shift then mask. Fix this by converting to use
SYS_FIELD_GET().

The only other field where the _MASK for this register is used is IminLine
which is at offset 0 so unaffected.

Fixes: 9a3634d02301 ("arm64/sysreg: Convert CTR_EL0 to automatic generation")
Reported-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/asm/cache.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
index ca9b487112cc..34256bda0da9 100644
--- a/arch/arm64/include/asm/cache.h
+++ b/arch/arm64/include/asm/cache.h
@@ -71,7 +71,7 @@ static __always_inline int icache_is_vpipt(void)
 
 static inline u32 cache_type_cwg(void)
 {
-	return (read_cpuid_cachetype() >> CTR_EL0_CWG_SHIFT) & CTR_EL0_CWG_MASK;
+	return SYS_FIELD_GET(CTR_EL0, CWG, read_cpuid_cachetype());
 }
 
 #define __read_mostly __section(".data..read_mostly")
-- 
2.30.2


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Re: [PATCH v2 0/3] arm64/cache: Fix cache_type_cwg() for register generation

[Will Deacon]

On Thu, 18 Aug 2022 22:36:10 +0100, Mark Brown wrote:
> Ard noticed that in converting CTR_EL0 to automatic generation we broke
> cache_type_cwg() since it was using a non-standard way of specifying
> _MASK that masks after rather than before shifting to retrieve the
> value. We could fix this directly in a single patch but there has been
> demand to also convert to use the SYS_FIELD_GET() accessor which
> requires a few preparatory patches to make that safe for direct use in
> cache.h.
> 
> [...]

Applied to arm64 (for-next/fixes), thanks!

[1/3] arm64/sysreg: Directly include bitfield.h
      https://git.kernel.org/arm64/c/02e483f8d414
[2/3] arm64/sysreg: Guard SYS_FIELD_ macros for asm
      https://git.kernel.org/arm64/c/a10edea4efbb
[3/3] arm64/cache: Fix cache_type_cwg() for register generation
      https://git.kernel.org/arm64/c/53d2d84a1f6d

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev

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