From: Rob Herring <robh@kernel.org>
To: Richard Zhu <hongxing.zhu@nxp.com>
Cc: p.zabel@pengutronix.de, l.stach@pengutronix.de,
bhelgaas@google.com, lorenzo.pieralisi@arm.com,
shawnguo@kernel.org, vkoul@kernel.org,
alexander.stein@ew.tq-group.com, marex@denx.de,
linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, kernel@pengutronix.de,
linux-imx@nxp.com
Subject: Re: [PATCH v3 2/6] dt-binding: phy: Add iMX8MP PCIe PHY binding
Date: Mon, 22 Aug 2022 13:07:13 -0500 [thread overview]
Message-ID: <20220822180713.GA75195-robh@kernel.org> (raw)
In-Reply-To: <1660806153-29001-3-git-send-email-hongxing.zhu@nxp.com>
On Thu, Aug 18, 2022 at 03:02:29PM +0800, Richard Zhu wrote:
> Add i.MX8MP PCIe PHY binding.
Explain the differences in h/w. The phy is connected to PERST#?
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---
> .../bindings/phy/fsl,imx8-pcie-phy.yaml | 16 +++++++++++++---
> 1 file changed, 13 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> index b6421eedece3..692783c7fd69 100644
> --- a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> @@ -16,6 +16,7 @@ properties:
> compatible:
> enum:
> - fsl,imx8mm-pcie-phy
> + - fsl,imx8mp-pcie-phy
>
> reg:
> maxItems: 1
> @@ -28,11 +29,16 @@ properties:
> - const: ref
>
> resets:
> - maxItems: 1
> + minItems: 1
> + maxItems: 2
>
> reset-names:
> - items:
> - - const: pciephy
> + oneOf:
> + - items: # for iMX8MM
> + - const: pciephy
> + - items: # for IMX8MP
> + - const: pciephy
> + - const: perst
This does the same thing:
minItems: 1
items:
- const: pciephy
- const: perst
>
> fsl,refclk-pad-mode:
> description: |
> @@ -60,6 +66,10 @@ properties:
> description: A boolean property indicating the CLKREQ# signal is
> not supported in the board design (optional)
>
> + power-domains:
> + description: PCIe PHY power domain (optional).
> + maxItems: 1
> +
> required:
> - "#phy-cells"
> - compatible
> --
> 2.25.1
>
>
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next prev parent reply other threads:[~2022-08-22 18:08 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-18 7:02 [PATCH v3 0/6] Add the iMX8MP PCIe support Richard Zhu
2022-08-18 7:02 ` [PATCH v3 1/6] reset: imx7: Add the iMX8MP PCIe PHY PERST support Richard Zhu
2022-08-18 8:50 ` Philipp Zabel
2022-08-18 10:53 ` Hongxing Zhu
2022-08-29 8:10 ` Lorenzo Pieralisi
2022-08-29 8:14 ` Hongxing Zhu
2022-08-18 7:02 ` [PATCH v3 2/6] dt-binding: phy: Add iMX8MP PCIe PHY binding Richard Zhu
2022-08-22 18:07 ` Rob Herring [this message]
2022-08-23 2:11 ` Hongxing Zhu
2022-08-24 9:15 ` Hongxing Zhu
2022-08-18 7:02 ` [PATCH v3 3/6] phy: freescale: imx8m-pcie: Add iMX8MP PCIe PHY support Richard Zhu
2022-08-18 7:02 ` [PATCH v3 4/6] arm64: dts: imx8mp: add the iMX8MP PCIe support Richard Zhu
2022-08-18 7:02 ` [PATCH v3 5/6] arm64: dts: imx8mp-evk: Add " Richard Zhu
2022-08-18 7:02 ` [PATCH v3 6/6] PCI: imx6: Add the iMX8MP " Richard Zhu
2022-08-18 9:20 ` [PATCH v3 0/6] " Marek Vasut
2022-08-18 10:53 ` Hongxing Zhu
2022-08-18 11:49 ` Marek Vasut
2022-08-25 12:23 ` Richard Leitner
2022-08-26 1:29 ` Hongxing Zhu
2022-08-26 6:22 ` Alexander Stein
2022-08-26 6:56 ` Hongxing Zhu
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