* [PATCH 0/2] MT8195: Add resets for PCIe controllers
@ 2022-06-29 10:52 AngeloGioacchino Del Regno
2022-06-29 10:52 ` [PATCH 1/2] dt-bindings: reset: mt8195: Add resets for PCIE controllers AngeloGioacchino Del Regno
2022-06-29 10:52 ` [PATCH 2/2] clk: mediatek: mt8195: Add reset idx for PCIe0 and PCIe1 AngeloGioacchino Del Regno
0 siblings, 2 replies; 6+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-06-29 10:52 UTC (permalink / raw)
To: mturquette
Cc: sboyd, matthias.bgg, p.zabel, robh+dt, krzysztof.kozlowski+dt,
angelogioacchino.delregno, wenst, chun-jie.chen, miles.chen,
rex-bc.chen, linux-clk, linux-arm-kernel, linux-mediatek,
linux-kernel, devicetree
The MediaTek PCIe driver supports resets from a reset controller and
they're essential for correct initialization of the PCIe controllers.
As a preparation for adding the PCIe nodes to mt8195, add the resets
to dt-bindings and infra_ao clock driver.
AngeloGioacchino Del Regno (2):
dt-bindings: reset: mt8195: Add resets for PCIE controllers
clk: mediatek: mt8195: Add reset idx for PCIe0 and PCIe1
drivers/clk/mediatek/clk-mt8195-infra_ao.c | 2 ++
include/dt-bindings/reset/mt8195-resets.h | 2 ++
2 files changed, 4 insertions(+)
--
2.35.1
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] dt-bindings: reset: mt8195: Add resets for PCIE controllers
2022-06-29 10:52 [PATCH 0/2] MT8195: Add resets for PCIe controllers AngeloGioacchino Del Regno
@ 2022-06-29 10:52 ` AngeloGioacchino Del Regno
2022-06-29 11:46 ` Krzysztof Kozlowski
2022-09-01 1:14 ` Stephen Boyd
2022-06-29 10:52 ` [PATCH 2/2] clk: mediatek: mt8195: Add reset idx for PCIe0 and PCIe1 AngeloGioacchino Del Regno
1 sibling, 2 replies; 6+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-06-29 10:52 UTC (permalink / raw)
To: mturquette
Cc: sboyd, matthias.bgg, p.zabel, robh+dt, krzysztof.kozlowski+dt,
angelogioacchino.delregno, wenst, chun-jie.chen, miles.chen,
rex-bc.chen, linux-clk, linux-arm-kernel, linux-mediatek,
linux-kernel, devicetree
Add the reset index for PCIe P0 and P1 (PCIe0, PCIe1) on MT8195.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
include/dt-bindings/reset/mt8195-resets.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
index c87ba621e72e..5471468c43b7 100644
--- a/include/dt-bindings/reset/mt8195-resets.h
+++ b/include/dt-bindings/reset/mt8195-resets.h
@@ -31,6 +31,8 @@
#define MT8195_INFRA_RST0_THERM_CTRL_SWRST 0
#define MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST 1
#define MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST 2
+#define MT8195_INFRA_RST2_PCIE_P0_SWRST 3
+#define MT8195_INFRA_RST2_PCIE_P1_SWRST 4
/* VDOSYS1 */
#define MT8195_VDOSYS1_SW0_RST_B_SMI_LARB2 0
--
2.35.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] dt-bindings: reset: mt8195: Add resets for PCIE controllers
2022-06-29 10:52 ` [PATCH 1/2] dt-bindings: reset: mt8195: Add resets for PCIE controllers AngeloGioacchino Del Regno
@ 2022-06-29 11:46 ` Krzysztof Kozlowski
2022-09-01 1:14 ` Stephen Boyd
1 sibling, 0 replies; 6+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-29 11:46 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, mturquette
Cc: sboyd, matthias.bgg, p.zabel, robh+dt, krzysztof.kozlowski+dt,
wenst, chun-jie.chen, miles.chen, rex-bc.chen, linux-clk,
linux-arm-kernel, linux-mediatek, linux-kernel, devicetree
On 29/06/2022 12:52, AngeloGioacchino Del Regno wrote:
> Add the reset index for PCIe P0 and P1 (PCIe0, PCIe1) on MT8195.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> include/dt-bindings/reset/mt8195-resets.h | 2 ++
> 1 file changed, 2 insertions(+)
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] dt-bindings: reset: mt8195: Add resets for PCIE controllers
2022-06-29 10:52 ` [PATCH 1/2] dt-bindings: reset: mt8195: Add resets for PCIE controllers AngeloGioacchino Del Regno
2022-06-29 11:46 ` Krzysztof Kozlowski
@ 2022-09-01 1:14 ` Stephen Boyd
1 sibling, 0 replies; 6+ messages in thread
From: Stephen Boyd @ 2022-09-01 1:14 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, mturquette
Cc: matthias.bgg, p.zabel, robh+dt, krzysztof.kozlowski+dt,
angelogioacchino.delregno, wenst, chun-jie.chen, miles.chen,
rex-bc.chen, linux-clk, linux-arm-kernel, linux-mediatek,
linux-kernel, devicetree
Quoting AngeloGioacchino Del Regno (2022-06-29 03:52:04)
> Add the reset index for PCIe P0 and P1 (PCIe0, PCIe1) on MT8195.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
Applied to clk-next
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/2] clk: mediatek: mt8195: Add reset idx for PCIe0 and PCIe1
2022-06-29 10:52 [PATCH 0/2] MT8195: Add resets for PCIe controllers AngeloGioacchino Del Regno
2022-06-29 10:52 ` [PATCH 1/2] dt-bindings: reset: mt8195: Add resets for PCIE controllers AngeloGioacchino Del Regno
@ 2022-06-29 10:52 ` AngeloGioacchino Del Regno
2022-09-01 1:14 ` Stephen Boyd
1 sibling, 1 reply; 6+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-06-29 10:52 UTC (permalink / raw)
To: mturquette
Cc: sboyd, matthias.bgg, p.zabel, robh+dt, krzysztof.kozlowski+dt,
angelogioacchino.delregno, wenst, chun-jie.chen, miles.chen,
rex-bc.chen, linux-clk, linux-arm-kernel, linux-mediatek,
linux-kernel, devicetree
Add the reset idx for PCIe P0, P1, located in infra_ao RST2 registers.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/clk/mediatek/clk-mt8195-infra_ao.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mt8195-infra_ao.c b/drivers/clk/mediatek/clk-mt8195-infra_ao.c
index 97657f255618..ce7ac16a2f42 100644
--- a/drivers/clk/mediatek/clk-mt8195-infra_ao.c
+++ b/drivers/clk/mediatek/clk-mt8195-infra_ao.c
@@ -193,6 +193,8 @@ static u16 infra_ao_rst_ofs[] = {
static u16 infra_ao_idx_map[] = {
[MT8195_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0,
+ [MT8195_INFRA_RST2_PCIE_P0_SWRST] = 2 * RST_NR_PER_BANK + 26,
+ [MT8195_INFRA_RST2_PCIE_P1_SWRST] = 2 * RST_NR_PER_BANK + 27,
[MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5,
[MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 10,
};
--
2.35.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 2/2] clk: mediatek: mt8195: Add reset idx for PCIe0 and PCIe1
2022-06-29 10:52 ` [PATCH 2/2] clk: mediatek: mt8195: Add reset idx for PCIe0 and PCIe1 AngeloGioacchino Del Regno
@ 2022-09-01 1:14 ` Stephen Boyd
0 siblings, 0 replies; 6+ messages in thread
From: Stephen Boyd @ 2022-09-01 1:14 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, mturquette
Cc: matthias.bgg, p.zabel, robh+dt, krzysztof.kozlowski+dt,
angelogioacchino.delregno, wenst, chun-jie.chen, miles.chen,
rex-bc.chen, linux-clk, linux-arm-kernel, linux-mediatek,
linux-kernel, devicetree
Quoting AngeloGioacchino Del Regno (2022-06-29 03:52:05)
> Add the reset idx for PCIe P0, P1, located in infra_ao RST2 registers.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
Applied to clk-next
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-09-01 1:15 UTC | newest]
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2022-06-29 10:52 [PATCH 0/2] MT8195: Add resets for PCIe controllers AngeloGioacchino Del Regno
2022-06-29 10:52 ` [PATCH 1/2] dt-bindings: reset: mt8195: Add resets for PCIE controllers AngeloGioacchino Del Regno
2022-06-29 11:46 ` Krzysztof Kozlowski
2022-09-01 1:14 ` Stephen Boyd
2022-06-29 10:52 ` [PATCH 2/2] clk: mediatek: mt8195: Add reset idx for PCIe0 and PCIe1 AngeloGioacchino Del Regno
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