From: Shawn Guo <shawnguo@kernel.org>
To: Li Yang <leoyang.li@nxp.com>
Cc: devicetree@vger.kernel.org, robh+dt@kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Po Liu <po.liu@nxp.com>,
Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Subject: Re: [PATCH 03/11] arm64: dts: ls1043a: use pcie aer/pme interrupts
Date: Mon, 5 Sep 2022 09:05:10 +0800 [thread overview]
Message-ID: <20220905010510.GO1728671@dragon> (raw)
In-Reply-To: <20220824223700.32442-4-leoyang.li@nxp.com>
On Wed, Aug 24, 2022 at 05:36:54PM -0500, Li Yang wrote:
> After the binding has been updated to include more specific interrupt
> definition, update the dts to use the more specific interrupt names.
>
> Signed-off-by: Po Liu <po.liu@nxp.com>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Signed-off-by: Li Yang <leoyang.li@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> index 3ba66b18de35..242fe8bfab17 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> @@ -883,9 +883,9 @@ pcie1: pcie@3400000 {
> reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
> <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
> reg-names = "regs", "config";
> - interrupts = <0 118 0x4>, /* controller interrupt */
> - <0 117 0x4>; /* PME interrupt */
> - interrupt-names = "intr", "pme";
> + interrupts = <0 117 0x4>,
> + <0 118 0x4>;
While at it, could you use IRQ_TYPE_LEVEL_HIGH for the polarity cell?
Shawn
> + interrupt-names = "pme", "aer";
> #address-cells = <3>;
> #size-cells = <2>;
> device_type = "pci";
> @@ -909,9 +909,9 @@ pcie2: pcie@3500000 {
> reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
> <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
> reg-names = "regs", "config";
> - interrupts = <0 128 0x4>,
> - <0 127 0x4>;
> - interrupt-names = "intr", "pme";
> + interrupts = <0 127 0x4>,
> + <0 128 0x4>;
> + interrupt-names = "pme", "aer";
> #address-cells = <3>;
> #size-cells = <2>;
> device_type = "pci";
> @@ -935,9 +935,9 @@ pcie3: pcie@3600000 {
> reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
> <0x50 0x00000000 0x0 0x00002000>; /* configuration space */
> reg-names = "regs", "config";
> - interrupts = <0 162 0x4>,
> - <0 161 0x4>;
> - interrupt-names = "intr", "pme";
> + interrupts = <0 161 0x4>,
> + <0 162 0x4>;
> + interrupt-names = "pme", "aer";
> #address-cells = <3>;
> #size-cells = <2>;
> device_type = "pci";
> --
> 2.37.1
>
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next prev parent reply other threads:[~2022-09-05 1:41 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-24 22:36 [PATCH 00/11] accumulated dts updates for ls1043a Li Yang
2022-08-24 22:36 ` [PATCH 01/11] arm64: dts: ls1043a: fix the wrong size of dcfg space Li Yang
2022-08-24 22:36 ` [PATCH 02/11] arm64: dts: ls1043a: Enable usb3-lpm-capable for usb3 node Li Yang
2022-08-24 22:36 ` [PATCH 03/11] arm64: dts: ls1043a: use pcie aer/pme interrupts Li Yang
2022-09-05 1:05 ` Shawn Guo [this message]
2022-08-24 22:36 ` [PATCH 04/11] arm64: dts: ls1043a: Add SCFG phandle for PCIe nodes Li Yang
2022-08-24 22:36 ` [PATCH 05/11] arm64: dts: ls1043a: Add big-endian property " Li Yang
2022-08-24 22:36 ` [PATCH 06/11] arm64: dts: ls1043a: add missing dma ranges property Li Yang
2022-08-24 22:36 ` [PATCH 07/11] arm64: dts: ls1043a: make dma-coherent global to the SoC Li Yang
2022-08-24 22:36 ` [PATCH 08/11] arm64: dts: ls1043a: add gpio based i2c recovery information Li Yang
2022-09-05 1:06 ` Shawn Guo
2022-08-24 22:37 ` [PATCH 09/11] arm64: dts: ls1043a: use a pseudo-bus to constrain usb and sata dma size Li Yang
2022-09-05 1:09 ` Shawn Guo
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