From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2F961C54EE9 for ; Wed, 7 Sep 2022 16:29:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+0NhUCt3WyVXJc7c26o9brVLwX/OG0FrOQDatR7lX+I=; b=mA87AoegtihLbC waS0aC+4nRnkONqoOuk4CcrKdioFPE8G9F9wUb6PMVrG6YTa028lAOMOLO2mBwxs5SwI5vMZRq6RB 7TwTHPwTJ4sKroWgyaipyg0XEUDCu4xtxGsgsdyFAyHHEnbebQ48xWndT1FKXRQBs3Y93Xo4QeJip 81WusFGNDQyzbgqRxuAXkQ0KmnrcNYY8B0krTpuDbR7jnhb7v8JBqcofZLyvDr/XYS78MGSRYpUCY i0s6AJBMp5cQj0924Q+eYnWP2ac58g8qYWrW0SHBdDbIQaT0c2yZVmvUt9LXeBAmnWpCuxz6L1seJ IMxuoCO7pb0zTkvLk/yQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oVxuc-007lfQ-2V; Wed, 07 Sep 2022 16:28:26 +0000 Received: from ams.source.kernel.org ([145.40.68.75]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oVxuY-007ldm-Dg for linux-arm-kernel@lists.infradead.org; Wed, 07 Sep 2022 16:28:23 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 40520B81E12; Wed, 7 Sep 2022 16:28:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B323AC433C1; Wed, 7 Sep 2022 16:28:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1662568099; bh=9WU7fv+LfDHNu49tRkbdlM5iTjSWANm4GZIMb+JGask=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=Pcphe9AfGAJu6bzwNDFltXCKpTSUJ3eqUCvqarHYazDTy/j5y7N9NOhdlc9KCDhWJ 5jS4AWgoYa0vG6oo5/cxaRsBfKQnrDnHDE6NWwbrN4N4vmBpeWRxRGmtZO4ZAyXXDr jVE+NeU5kk9nFOPHESOnSJHJ2MiHcoikacPeWjR9BNm1FKGBzPg8eUrIO3Ww8jH9k3 wMSReb2fzfxYKt6jqgeK5Qjl0ktv3R/zb3Dh20AYe2ocmnO7q0w8KPAaRBMR0FWn17 g6c4ySddyHHFFqGsqSf6Kk1XFwksTuV16m7Fa6l8IGL5VEFehrly2HEscagjXDU24C dU23cypoUPxpQ== Date: Wed, 7 Sep 2022 17:28:13 +0100 From: Will Deacon To: Christoph Hellwig Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas , Mark Rutland , Robin Murphy , Ard Biesheuvel Subject: Re: [PATCH] arm64: dma: Drop cache invalidation from arch_dma_prep_coherent() Message-ID: <20220907162813.GB30558@willie-the-truck> References: <20220823122111.17439-1-will@kernel.org> <20220907090305.GA30704@lst.de> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220907090305.GA30704@lst.de> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220907_092822_652086_FEF39011 X-CRM114-Status: GOOD ( 27.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Sep 07, 2022 at 11:03:05AM +0200, Christoph Hellwig wrote: > On Tue, Aug 23, 2022 at 01:21:11PM +0100, Will Deacon wrote: > > arch_dma_prep_coherent() is called when preparing a non-cacheable region > > for a consistent DMA buffer allocation. Since the buffer pages may > > previously have been written via a cacheable mapping and consequently > > allocated as dirty cachelines, the purpose of this function is to remove > > these dirty lines from the cache, writing them back so that the > > non-coherent device is able to see them. > > Yes. > > > I'm slightly wary about this change as other architectures seem to do > > clean+invalidate here, but I'd like to hear what others think in any > > case. > > If arm64 is fine with having clean but present cachelines when creating > an uncached mapping for a cache line, the invalidate is not required. > > But isn't it better for the cache if these by definition useless > cachelines get evicted? > > My biggest concern here is that we're now moving from consolidating > these semantics in all the different architectures to different ones, > making a centralization of the policies even harder. I definitely wouldn't object to a pointless invalidation if it helped with consolidation, and we could add a comment to the arch code to that effect. At the moment, however, I can't imagine what this consolidation would look like -- at the end of the day we're going to need to dip into the arch for the cache op. Do you have a branch, or is it a longer-term goal? Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel