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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id p21-20020a9d76d5000000b006396521c804sm4665634otl.55.2022.09.12.08.01.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Sep 2022 08:01:56 -0700 (PDT) Received: (nullmailer pid 1293608 invoked by uid 1000); Mon, 12 Sep 2022 15:01:55 -0000 Date: Mon, 12 Sep 2022 10:01:55 -0500 From: Rob Herring To: Serge Semin Cc: Michail Ivanov , James Morse , Pavel Parkhomenko , Tony Luck , devicetree@vger.kernel.org, Dinh Nguyen , Robert Richter , Punnaiah Choudary Kalluri , Manish Narani , Michal Simek , Rob Herring , Krzysztof Kozlowski , linux-edac@vger.kernel.org, Serge Semin , linux-kernel@vger.kernel.org, Mauro Carvalho Chehab , Alexey Malahov , linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski , Borislav Petkov Subject: Re: [PATCH v2 04/15] dt-bindings: memory: Add Baikal-T1 DDRC DT-schema Message-ID: <20220912150155.GA1293565-robh@kernel.org> References: <20220910195659.11843-1-Sergey.Semin@baikalelectronics.ru> <20220910195659.11843-5-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220910195659.11843-5-Sergey.Semin@baikalelectronics.ru> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220912_080159_625747_DF089D50 X-CRM114-Status: GOOD ( 14.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, 10 Sep 2022 22:56:48 +0300, Serge Semin wrote: > Baikal-T1 DDR controller is based on the DW uMCTL2 DDRC IP-core v2.51a > with up to DDR3 protocol capability and 32-bit data bus + 8-bit ECC. There > are individual IRQs for each ECC and DFI events. The dedicated scrubber > clock source is absent since it's fully synchronous to the core clock. > In addition to that the DFI-DDR PHY CSRs can be accessed via a separate > registers space. > > Signed-off-by: Serge Semin > > --- > > Changelog v2: > - Keep the alphabetically ordered compatible strings list. (@Krzysztof) > - Fix grammar nitpicks in the patch log. (@Krzysztof) > - Drop the PHY CSR region. (@Rob) > - Move the device bindings to the separate DT-schema. > --- > .../memory-controllers/baikal,bt1-ddrc.yaml | 91 +++++++++++++++++++ > 1 file changed, 91 insertions(+) > create mode 100644 Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml > Reviewed-by: Rob Herring _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel