From: Will Deacon <will@kernel.org>
To: Jean-Philippe Brucker <jean-philippe@linaro.org>, joro@8bytes.org
Cc: robin.murphy@arm.com, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org,
linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] dt-bindings: iommu: arm,smmu-v3: Relax order of interrupt names
Date: Thu, 22 Sep 2022 22:08:56 +0100 [thread overview]
Message-ID: <20220922210855.GC12945@willie-the-truck> (raw)
In-Reply-To: <20220916133145.1910549-1-jean-philippe@linaro.org>
On Fri, Sep 16, 2022 at 02:31:47PM +0100, Jean-Philippe Brucker wrote:
> The QEMU devicetree uses a different order for SMMUv3 interrupt names,
> and there isn't a good reason for enforcing a specific order. Since all
> interrupt lines are optional, operating systems should not expect a
> fixed interrupt array layout; they should instead match each interrupt
> to its name individually. Besides, as a result of commit e4783856a2e8
> ("dt-bindings: iommu: arm,smmu-v3: make PRI IRQ optional"), "cmdq-sync"
> and "priq" are already permutable. Relax the interrupt-names array
> entirely by allowing any permutation, incidentally making the schema
> more readable.
>
> Note that dt-validate won't allow duplicate names here so we don't need
> to specify maxItems or add additional checks, it's quite neat.
>
> Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
> ---
> .../devicetree/bindings/iommu/arm,smmu-v3.yaml | 15 +++++----------
> 1 file changed, 5 insertions(+), 10 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> index c57a53d87e4e..75fcf4cb52d9 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> @@ -39,16 +39,11 @@ properties:
> any others.
> - minItems: 1
> items:
> - - enum:
> - - eventq # Event Queue not empty
> - - gerror # Global Error activated
> - - const: gerror
> - - enum:
> - - cmdq-sync # CMD_SYNC complete
> - - priq # PRI Queue not empty
> - - enum:
> - - cmdq-sync
> - - priq
> + enum:
> + - eventq # Event Queue not empty
> + - gerror # Global Error activated
> + - cmdq-sync # CMD_SYNC complete
> + - priq # PRI Queue not empty
>
> '#iommu-cells':
> const: 1
Acked-by: Will Deacon <will@kernel.org>
Joerg -- please can you take this one directly for 6.1? I don't actually
have any other SMMU patches queued, so it doesn't seem worth sending a pull
request just for this.
Cheers,
Will
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next prev parent reply other threads:[~2022-09-22 21:09 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-16 13:31 [PATCH] dt-bindings: iommu: arm,smmu-v3: Relax order of interrupt names Jean-Philippe Brucker
2022-09-22 12:54 ` Krzysztof Kozlowski
2022-09-22 21:08 ` Will Deacon [this message]
2022-09-26 12:06 ` Joerg Roedel
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