From: Bjorn Helgaas <helgaas@kernel.org>
To: Vadym Kochan <vadym.kochan@plvision.eu>
Cc: "Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
"Elad Nachman" <enachman@marvell.com>,
"Yuval Shaia" <yshaia@marvell.com>, raza <raza@marvell.com>
Subject: Re: [PATCH 1/2] PCI: armada8k: Add AC5 SoC support
Date: Thu, 6 Oct 2022 11:05:58 -0500 [thread overview]
Message-ID: <20221006160558.GA2467717@bhelgaas> (raw)
In-Reply-To: <20221006111110.8574-2-vadym.kochan@plvision.eu>
On Thu, Oct 06, 2022 at 02:11:09PM +0300, Vadym Kochan wrote:
> From: raza <raza@marvell.com>
>
> pcie-armada8k driver is utilized to serve also AC5.
> Driver assumes interrupt mask registers are located in the same address in
> both CPUs.
> This assumption is incorrect - fix it for AC5.
Rewrap into one paragraph or add blank lines between paragraphs.
> Co-developed-by: Yuval Shaia <yshaia@marvell.com>
> Signed-off-by: Yuval Shaia <yshaia@marvell.com>
> Signed-off-by: raza <raza@marvell.com>
Real name for "raza"? See this:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?id=v5.18#n407
> + /* Set the PCIe master AxCache attributes */
> + dw_pcie_writel_dbi(pci, PCIE_ARCACHE_TRC_REG, ARCACHE_DEFAULT_VALUE);
> + dw_pcie_writel_dbi(pci, PCIE_AWCACHE_TRC_REG, AWCACHE_DEFAULT_VALUE);
Rewrap to fit in 80 columns like the rest of the file.
> +static u32 ac5_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
> + u32 reg, size_t size)
> +{
> + u32 val;
> +
> + /* Handle AC5 ATU access */
> + if ((reg & ~0xfffff) == 0x300000) {
> + reg &= 0xfffff;
> + reg = 0xc000 | (0x200 * (reg >> 9)) | (reg & 0xff);
> + } else if ((reg & 0xfffff000) == PCIE_VENDOR_REGS_OFFSET)
> + reg += 0x8000; /* PCIE_VENDOR_REGS_OFFSET in ac5 is 0x10000 */
There are lots of magic numbers here; looks like there should be some
#defines or something.
Bjorn
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next prev parent reply other threads:[~2022-10-06 16:07 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-06 11:11 [PATCH 0/2] PCI: armada8k: Add support for AC5 SoC Vadym Kochan
2022-10-06 11:11 ` [PATCH 1/2] PCI: armada8k: Add AC5 SoC support Vadym Kochan
2022-10-06 16:05 ` Bjorn Helgaas [this message]
2022-10-06 11:11 ` [PATCH 2/2] PCI: armada8k: Add MSI support for AC5 SoC Vadym Kochan
2022-10-06 16:06 ` Bjorn Helgaas
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