[PATCH v3 0/3] PCI: add 4x lane support for pci-j721e controllers

[PATCH v3 0/3] PCI: add 4x lane support for pci-j721e controllers

[Matt Ranostay]

Adding of dditional support to Cadence PCIe controller (i.e. pci-j721e.c)
for up to 4x lanes, and reworking of driver to define maximum lanes per
board configuration.

Changes from v1:
* Reworked 'PCI: j721e: Add PCIe 4x lane selection support' to not cause
  regressions on 1-2x lane platforms

Changes from v2:
* Correct dev_warn format string from %d to %u since lane count is a unsigned
  integer
* Update CC list

Matt Ranostay (3):
  PCI: j721e: Add PCIe 4x lane selection support
  PCI: j721e: Add per platform maximum lane settings
  PCI: j721e: Add warnings on num-lanes misconfiguration

 drivers/pci/controller/cadence/pci-j721e.c | 27 ++++++++++++++++++----
 1 file changed, 22 insertions(+), 5 deletions(-)

-- 
2.38.GIT


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[PATCH v3 1/3] PCI: j721e: Add PCIe 4x lane selection support

[Matt Ranostay]

Add support for setting of two-bit field that allows selection of 4x
lane PCIe which was previously limited to only 2x lanes.

Signed-off-by: Matt Ranostay <mranostay@ti.com>
---
 drivers/pci/controller/cadence/pci-j721e.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index a82f845cc4b5..d9b1527421c3 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -43,7 +43,6 @@ enum link_status {
 };
 
 #define J721E_MODE_RC			BIT(7)
-#define LANE_COUNT_MASK			BIT(8)
 #define LANE_COUNT(n)			((n) << 8)
 
 #define GENERATION_SEL_MASK		GENMASK(1, 0)
@@ -207,11 +206,15 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
 {
 	struct device *dev = pcie->cdns_pcie->dev;
 	u32 lanes = pcie->num_lanes;
+	u32 mask = GENMASK(8, 8);
 	u32 val = 0;
 	int ret;
 
+	if (lanes == 4)
+		mask = GENMASK(9, 8);
+
 	val = LANE_COUNT(lanes - 1);
-	ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val);
+	ret = regmap_update_bits(syscon, offset, mask, val);
 	if (ret)
 		dev_err(dev, "failed to set link count\n");
 
-- 
2.38.GIT


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[PATCH v3 2/3] PCI: j721e: Add per platform maximum lane settings

[Matt Ranostay]

Various platforms have different maximum amount of lanes that
can be selected. Add max_lanes to struct j721e_pcie to allow
for error checking on num-lanes selection from device tree.

Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
 drivers/pci/controller/cadence/pci-j721e.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index d9b1527421c3..0a537f2d5078 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -47,8 +47,6 @@ enum link_status {
 
 #define GENERATION_SEL_MASK		GENMASK(1, 0)
 
-#define MAX_LANES			2
-
 struct j721e_pcie {
 	struct cdns_pcie	*cdns_pcie;
 	struct clk		*refclk;
@@ -71,6 +69,7 @@ struct j721e_pcie_data {
 	unsigned int		quirk_disable_flr:1;
 	u32			linkdown_irq_regfield;
 	unsigned int		byte_access_allowed:1;
+	unsigned int		max_lanes;
 };
 
 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
@@ -294,11 +293,13 @@ static const struct j721e_pcie_data j721e_pcie_rc_data = {
 	.quirk_retrain_flag = true,
 	.byte_access_allowed = false,
 	.linkdown_irq_regfield = LINK_DOWN,
+	.max_lanes = 2,
 };
 
 static const struct j721e_pcie_data j721e_pcie_ep_data = {
 	.mode = PCI_MODE_EP,
 	.linkdown_irq_regfield = LINK_DOWN,
+	.max_lanes = 2,
 };
 
 static const struct j721e_pcie_data j7200_pcie_rc_data = {
@@ -306,23 +307,27 @@ static const struct j721e_pcie_data j7200_pcie_rc_data = {
 	.quirk_detect_quiet_flag = true,
 	.linkdown_irq_regfield = J7200_LINK_DOWN,
 	.byte_access_allowed = true,
+	.max_lanes = 4,
 };
 
 static const struct j721e_pcie_data j7200_pcie_ep_data = {
 	.mode = PCI_MODE_EP,
 	.quirk_detect_quiet_flag = true,
 	.quirk_disable_flr = true,
+	.max_lanes = 4,
 };
 
 static const struct j721e_pcie_data am64_pcie_rc_data = {
 	.mode = PCI_MODE_RC,
 	.linkdown_irq_regfield = J7200_LINK_DOWN,
 	.byte_access_allowed = true,
+	.max_lanes = 1,
 };
 
 static const struct j721e_pcie_data am64_pcie_ep_data = {
 	.mode = PCI_MODE_EP,
 	.linkdown_irq_regfield = J7200_LINK_DOWN,
+	.max_lanes = 1,
 };
 
 static const struct of_device_id of_j721e_pcie_match[] = {
@@ -436,7 +441,7 @@ static int j721e_pcie_probe(struct platform_device *pdev)
 	pcie->user_cfg_base = base;
 
 	ret = of_property_read_u32(node, "num-lanes", &num_lanes);
-	if (ret || num_lanes > MAX_LANES)
+	if (ret || num_lanes > data->max_lanes)
 		num_lanes = 1;
 	pcie->num_lanes = num_lanes;
 
-- 
2.38.GIT


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[PATCH v3 3/3] PCI: j721e: Add warnings on num-lanes misconfiguration

[Matt Ranostay]

Added dev_warn messages to alert of devicetree misconfigurations
for incorrect num-lanes setting, or the lack of one being defined.

Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
 drivers/pci/controller/cadence/pci-j721e.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index 0a537f2d5078..2922be2ac4e1 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -441,8 +441,17 @@ static int j721e_pcie_probe(struct platform_device *pdev)
 	pcie->user_cfg_base = base;
 
 	ret = of_property_read_u32(node, "num-lanes", &num_lanes);
-	if (ret || num_lanes > data->max_lanes)
+	if (ret) {
+		dev_warn(dev, "no num-lanes defined, defaulting to 1\n");
 		num_lanes = 1;
+	}
+
+	if (num_lanes > data->max_lanes) {
+		dev_warn(dev, "defined num-lanes %u is greater than the "
+			      "allowed maximum of %u, defaulting to 1\n",
+			      num_lanes, data->max_lanes);
+		num_lanes = 1;
+	}
 	pcie->num_lanes = num_lanes;
 
 	if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
-- 
2.38.GIT


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Re: [PATCH v3 3/3] PCI: j721e: Add warnings on num-lanes misconfiguration

[Bjorn Helgaas]

On Wed, Oct 19, 2022 at 06:29:11PM -0700, Matt Ranostay wrote:
> Added dev_warn messages to alert of devicetree misconfigurations
> for incorrect num-lanes setting, or the lack of one being defined.

s/Added/Add/ if you repost for anything else:

  https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?id=v5.16#n95

> +		dev_warn(dev, "defined num-lanes %u is greater than the "
> +			      "allowed maximum of %u, defaulting to 1\n",
> +			      num_lanes, data->max_lanes);

Don't repost just for this, but I generally prefer to keep printf
strings intact even if they exceed 80 columns, because it makes it
easier for someone to grep for something like
"greater than the allowed".

> +		num_lanes = 1;
> +	}
>  	pcie->num_lanes = num_lanes;
>  
>  	if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
> -- 
> 2.38.GIT
> 

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Re: [PATCH v3 1/3] PCI: j721e: Add PCIe 4x lane selection support

[Vignesh Raghavendra]

Hi Matt,

On 20/10/22 6:59 am, Matt Ranostay wrote:
> Add support for setting of two-bit field that allows selection of 4x
> lane PCIe which was previously limited to only 2x lanes.
> 
> Signed-off-by: Matt Ranostay <mranostay@ti.com>
> ---
>  drivers/pci/controller/cadence/pci-j721e.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> index a82f845cc4b5..d9b1527421c3 100644
> --- a/drivers/pci/controller/cadence/pci-j721e.c
> +++ b/drivers/pci/controller/cadence/pci-j721e.c
> @@ -43,7 +43,6 @@ enum link_status {
>  };
>  
>  #define J721E_MODE_RC			BIT(7)
> -#define LANE_COUNT_MASK			BIT(8)
>  #define LANE_COUNT(n)			((n) << 8)
>  
>  #define GENERATION_SEL_MASK		GENMASK(1, 0)
> @@ -207,11 +206,15 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
>  {
>  	struct device *dev = pcie->cdns_pcie->dev;
>  	u32 lanes = pcie->num_lanes;
> +	u32 mask = GENMASK(8, 8);
>  	u32 val = 0;
>  	int ret;
>  
> +	if (lanes == 4)
> +		mask = GENMASK(9, 8);


Shouldn't we decide "mask" based on max_lanes added in 2/3 (ie how many
lanes HW can support and thus width of this bit field) instead of
num_lanes? Hypothetically, what if bootloader / other entity has set MSb
but Linux is restricted to 2 lanes in DT?

> +
>  	val = LANE_COUNT(lanes - 1);
> -	ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val);
> +	ret = regmap_update_bits(syscon, offset, mask, val);
>  	if (ret)
>  		dev_err(dev, "failed to set link count\n");
>  

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Re: [PATCH v3 1/3] PCI: j721e: Add PCIe 4x lane selection support

[Matt Ranostay]

On Tue, Oct 25, 2022 at 05:23:20PM +0530, Vignesh Raghavendra wrote:
> Hi Matt,
> 
> On 20/10/22 6:59 am, Matt Ranostay wrote:
> > Add support for setting of two-bit field that allows selection of 4x
> > lane PCIe which was previously limited to only 2x lanes.
> > 
> > Signed-off-by: Matt Ranostay <mranostay@ti.com>
> > ---
> >  drivers/pci/controller/cadence/pci-j721e.c | 7 +++++--
> >  1 file changed, 5 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> > index a82f845cc4b5..d9b1527421c3 100644
> > --- a/drivers/pci/controller/cadence/pci-j721e.c
> > +++ b/drivers/pci/controller/cadence/pci-j721e.c
> > @@ -43,7 +43,6 @@ enum link_status {
> >  };
> >  
> >  #define J721E_MODE_RC			BIT(7)
> > -#define LANE_COUNT_MASK			BIT(8)
> >  #define LANE_COUNT(n)			((n) << 8)
> >  
> >  #define GENERATION_SEL_MASK		GENMASK(1, 0)
> > @@ -207,11 +206,15 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
> >  {
> >  	struct device *dev = pcie->cdns_pcie->dev;
> >  	u32 lanes = pcie->num_lanes;
> > +	u32 mask = GENMASK(8, 8);
> >  	u32 val = 0;
> >  	int ret;
> >  
> > +	if (lanes == 4)
> > +		mask = GENMASK(9, 8);
> 
> 
> Shouldn't we decide "mask" based on max_lanes added in 2/3 (ie how many
> lanes HW can support and thus width of this bit field) instead of
> num_lanes? Hypothetically, what if bootloader / other entity has set MSb
> but Linux is restricted to 2 lanes in DT?

Ah yes that is a very good point, and the mask should be based on max_lanes.

Will fix up in v4...

- Matt

> 
> > +
> >  	val = LANE_COUNT(lanes - 1);
> > -	ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val);
> > +	ret = regmap_update_bits(syscon, offset, mask, val);
> >  	if (ret)
> >  		dev_err(dev, "failed to set link count\n");
> >  

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