* [PATCH 1/8] arm64: cpufeature: Fix the visibility of compat hwcaps
2022-10-26 5:58 [PATCH 0/8] arm64: Expose compat Armv8 AArch32 features Amit Daniel Kachhap
@ 2022-10-26 5:58 ` Amit Daniel Kachhap
2022-10-26 15:15 ` James Morse
2022-11-01 19:07 ` Catalin Marinas
2022-10-26 5:58 ` [PATCH 2/8] arm64: Add compat hwcap FPHP and ASIMDHP Amit Daniel Kachhap
` (6 subsequent siblings)
7 siblings, 2 replies; 15+ messages in thread
From: Amit Daniel Kachhap @ 2022-10-26 5:58 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Catalin Marinas, Will Deacon, Amit Daniel Kachhap, James Morse
Commit 237405ebef58 ("arm64: cpufeature: Force HWCAP to be based on the
sysreg visible to user-space") forced the hwcaps to use sanitised
user-space view of the id registers. However, the ID register structures
used to select few compat cpufeatures (vfp, crc32, ...) are masked and
hence such hwcaps do not appear in /proc/cpuinfo anymore for PER_LINUX32
personality.
Add the ID register structures explicitly and set them as visible for
the compat hwcaps.
Fixes: 237405ebef58 ("arm64: cpufeature: Force HWCAP to be based on the sysreg visible to user-space")
Cc: James Morse <james.morse@arm.com>
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
---
arch/arm64/kernel/cpufeature.c | 36 ++++++++++++++++++++++++++++------
1 file changed, 30 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 6062454a9067..43e5b43ef550 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -428,6 +428,30 @@ static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
ARM64_FTR_END,
};
+static const struct arm64_ftr_bits ftr_mvfr0[] = {
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPROUND_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSHVEC_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSQRT_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPDIVIDE_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPTRAP_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPDP_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSP_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_SIMD_SHIFT, 4, 0),
+ ARM64_FTR_END,
+};
+
+static const struct arm64_ftr_bits ftr_mvfr1[] = {
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDFMAC_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPHP_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDHP_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDSP_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDINT_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDLS_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPDNAN_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPFTZ_SHIFT, 4, 0),
+ ARM64_FTR_END,
+};
+
static const struct arm64_ftr_bits ftr_mvfr2[] = {
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0),
@@ -458,10 +482,10 @@ static const struct arm64_ftr_bits ftr_id_isar0[] = {
static const struct arm64_ftr_bits ftr_id_isar5[] = {
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
ARM64_FTR_END,
};
@@ -645,8 +669,8 @@ static const struct __ftr_reg_entry {
ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),
/* Op1 = 0, CRn = 0, CRm = 3 */
- ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
- ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
+ ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0),
+ ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1),
ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1),
--
2.17.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 1/8] arm64: cpufeature: Fix the visibility of compat hwcaps
2022-10-26 5:58 ` [PATCH 1/8] arm64: cpufeature: Fix the visibility of compat hwcaps Amit Daniel Kachhap
@ 2022-10-26 15:15 ` James Morse
2022-11-02 10:47 ` Amit Kachhap
2022-11-01 19:07 ` Catalin Marinas
1 sibling, 1 reply; 15+ messages in thread
From: James Morse @ 2022-10-26 15:15 UTC (permalink / raw)
To: Amit Daniel Kachhap, linux-arm-kernel
Cc: Catalin Marinas, Will Deacon, Suzuki K Poulose
Hi Amit,
(CC: +Suzuki)
On 26/10/2022 06:58, Amit Daniel Kachhap wrote:
> Commit 237405ebef58 ("arm64: cpufeature: Force HWCAP to be based on the
> sysreg visible to user-space") forced the hwcaps to use sanitised
> user-space view of the id registers. However, the ID register structures
> used to select few compat cpufeatures (vfp, crc32, ...) are masked and
> hence such hwcaps do not appear in /proc/cpuinfo anymore for PER_LINUX32
> personality.
Oops - I didn't check the 32bit ones. Thanks for catching this!
> Add the ID register structures explicitly and set them as visible for
> the compat hwcaps.
While 32bit user-space can't access these, 64bit with the personality set now can.
I don't think that's a problem.
Is there a separate posting of this patch on its own? (do I need to reply there too?)
Mixing fixes with a new-feature series makes the maintainers job harder. Its best to post
fixes separately so they can be treated more urgently than features.
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 6062454a9067..43e5b43ef550 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -428,6 +428,30 @@ static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
> ARM64_FTR_END,
> };
>
> +static const struct arm64_ftr_bits ftr_mvfr0[] = {
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPROUND_SHIFT, 4, 0),
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSHVEC_SHIFT, 4, 0),
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSQRT_SHIFT, 4, 0),
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPDIVIDE_SHIFT, 4, 0),
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPTRAP_SHIFT, 4, 0),
> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPDP_SHIFT, 4, 0),
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSP_SHIFT, 4, 0),
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_SIMD_SHIFT, 4, 0),
> + ARM64_FTR_END,
> +};
> +
> +static const struct arm64_ftr_bits ftr_mvfr1[] = {
> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDFMAC_SHIFT, 4, 0),
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPHP_SHIFT, 4, 0),
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDHP_SHIFT, 4, 0),
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDSP_SHIFT, 4, 0),
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDINT_SHIFT, 4, 0),
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDLS_SHIFT, 4, 0),
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPDNAN_SHIFT, 4, 0),
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPFTZ_SHIFT, 4, 0),
> + ARM64_FTR_END,
> +};
As these two no longer use ftr_generic_32bits[], could you update the comment above
ftr_generic_32bits[] which lists the id registers that use it?
> static const struct arm64_ftr_bits ftr_mvfr2[] = {
> ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0),
> ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0),
> @@ -458,10 +482,10 @@ static const struct arm64_ftr_bits ftr_id_isar0[] = {
>
> static const struct arm64_ftr_bits ftr_id_isar5[] = {
> ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
> - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
> - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
> - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
> - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
> ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
> ARM64_FTR_END,
> };
> @@ -645,8 +669,8 @@ static const struct __ftr_reg_entry {
> ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),
>
> /* Op1 = 0, CRn = 0, CRm = 3 */
> - ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
> - ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
> + ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0),
> + ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1),
> ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
> ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
> ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1),
Reviewed-by: James Morse <james.morse@arm.com>
Thanks,
James
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^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 1/8] arm64: cpufeature: Fix the visibility of compat hwcaps
2022-10-26 15:15 ` James Morse
@ 2022-11-02 10:47 ` Amit Kachhap
0 siblings, 0 replies; 15+ messages in thread
From: Amit Kachhap @ 2022-11-02 10:47 UTC (permalink / raw)
To: James Morse, linux-arm-kernel
Cc: Catalin Marinas, Will Deacon, Suzuki K Poulose
Hi,
On 10/26/22 20:45, James Morse wrote:
> Hi Amit,
>
> (CC: +Suzuki)
>
> On 26/10/2022 06:58, Amit Daniel Kachhap wrote:
>> Commit 237405ebef58 ("arm64: cpufeature: Force HWCAP to be based on the
>> sysreg visible to user-space") forced the hwcaps to use sanitised
>> user-space view of the id registers. However, the ID register structures
>> used to select few compat cpufeatures (vfp, crc32, ...) are masked and
>> hence such hwcaps do not appear in /proc/cpuinfo anymore for PER_LINUX32
>> personality.
>
> Oops - I didn't check the 32bit ones. Thanks for catching this!
>
>
>> Add the ID register structures explicitly and set them as visible for
>> the compat hwcaps.
>
> While 32bit user-space can't access these, 64bit with the personality set now can.
> I don't think that's a problem.
ok, Nice that this patch fixes other issues also which I didn't thought
about.
>
>
> Is there a separate posting of this patch on its own? (do I need to reply there too?)
> Mixing fixes with a new-feature series makes the maintainers job harder. Its best to post
> fixes separately so they can be treated more urgently than features.
>
>
>> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
>> index 6062454a9067..43e5b43ef550 100644
>> --- a/arch/arm64/kernel/cpufeature.c
>> +++ b/arch/arm64/kernel/cpufeature.c
>> @@ -428,6 +428,30 @@ static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
>> ARM64_FTR_END,
>> };
>>
>> +static const struct arm64_ftr_bits ftr_mvfr0[] = {
>> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPROUND_SHIFT, 4, 0),
>> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSHVEC_SHIFT, 4, 0),
>> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSQRT_SHIFT, 4, 0),
>> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPDIVIDE_SHIFT, 4, 0),
>> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPTRAP_SHIFT, 4, 0),
>> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPDP_SHIFT, 4, 0),
>> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSP_SHIFT, 4, 0),
>> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_SIMD_SHIFT, 4, 0),
>> + ARM64_FTR_END,
>> +};
>> +
>> +static const struct arm64_ftr_bits ftr_mvfr1[] = {
>> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDFMAC_SHIFT, 4, 0),
>> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPHP_SHIFT, 4, 0),
>> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDHP_SHIFT, 4, 0),
>> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDSP_SHIFT, 4, 0),
>> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDINT_SHIFT, 4, 0),
>> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDLS_SHIFT, 4, 0),
>> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPDNAN_SHIFT, 4, 0),
>> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPFTZ_SHIFT, 4, 0),
>> + ARM64_FTR_END,
>> +};
>
> As these two no longer use ftr_generic_32bits[], could you update the comment above
> ftr_generic_32bits[] which lists the id registers that use it?
I just send the v2 with your suggestion. Looks like comment were already
inconsistent.
>
>
>> static const struct arm64_ftr_bits ftr_mvfr2[] = {
>> ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0),
>> ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0),
>> @@ -458,10 +482,10 @@ static const struct arm64_ftr_bits ftr_id_isar0[] = {
>>
>> static const struct arm64_ftr_bits ftr_id_isar5[] = {
>> ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
>> - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
>> - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
>> - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
>> - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
>> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
>> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
>> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
>> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
>> ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
>> ARM64_FTR_END,
>> };
>> @@ -645,8 +669,8 @@ static const struct __ftr_reg_entry {
>> ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),
>>
>> /* Op1 = 0, CRn = 0, CRm = 3 */
>> - ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
>> - ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
>> + ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0),
>> + ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1),
>> ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
>> ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
>> ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1),
>
> Reviewed-by: James Morse <james.morse@arm.com>
Thanks for reviewing.
Amit
>
>
> Thanks,
>
> James
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/8] arm64: cpufeature: Fix the visibility of compat hwcaps
2022-10-26 5:58 ` [PATCH 1/8] arm64: cpufeature: Fix the visibility of compat hwcaps Amit Daniel Kachhap
2022-10-26 15:15 ` James Morse
@ 2022-11-01 19:07 ` Catalin Marinas
1 sibling, 0 replies; 15+ messages in thread
From: Catalin Marinas @ 2022-11-01 19:07 UTC (permalink / raw)
To: Amit Daniel Kachhap; +Cc: linux-arm-kernel, Will Deacon, James Morse
Hi Amit,
On Wed, Oct 26, 2022 at 11:28:06AM +0530, Amit Kachhap wrote:
> Commit 237405ebef58 ("arm64: cpufeature: Force HWCAP to be based on the
> sysreg visible to user-space") forced the hwcaps to use sanitised
> user-space view of the id registers. However, the ID register structures
> used to select few compat cpufeatures (vfp, crc32, ...) are masked and
> hence such hwcaps do not appear in /proc/cpuinfo anymore for PER_LINUX32
> personality.
>
> Add the ID register structures explicitly and set them as visible for
> the compat hwcaps.
>
> Fixes: 237405ebef58 ("arm64: cpufeature: Force HWCAP to be based on the sysreg visible to user-space")
> Cc: James Morse <james.morse@arm.com>
> Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
As James mentioned, could you please post this as a separate patch (and
update it with some of the comments that James had). Unless it was
posted and I missed it.
Thanks.
--
Catalin
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^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 2/8] arm64: Add compat hwcap FPHP and ASIMDHP
2022-10-26 5:58 [PATCH 0/8] arm64: Expose compat Armv8 AArch32 features Amit Daniel Kachhap
2022-10-26 5:58 ` [PATCH 1/8] arm64: cpufeature: Fix the visibility of compat hwcaps Amit Daniel Kachhap
@ 2022-10-26 5:58 ` Amit Daniel Kachhap
2022-11-09 18:00 ` Will Deacon
2022-10-26 5:58 ` [PATCH 3/8] arm64: Add compat hwcap ASIMDDP Amit Daniel Kachhap
` (5 subsequent siblings)
7 siblings, 1 reply; 15+ messages in thread
From: Amit Daniel Kachhap @ 2022-10-26 5:58 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Catalin Marinas, Will Deacon, Amit Daniel Kachhap
These hwcaps are earlier added for 32-bit native arm kernel and hence the
corresponding changes added in 32-bit compat arm64 kernel for similar
userspace interface. Floating point half-precision (FPHP) and Advanced
SIMD half-precision (ASIMDHP) represent the Armv8 FP16 feature extension
and is already advertised in arm64 kernel.
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
---
arch/arm64/include/asm/hwcap.h | 2 ++
arch/arm64/kernel/cpufeature.c | 6 ++++--
arch/arm64/kernel/cpuinfo.c | 2 ++
3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h
index 298b386d3ebe..a3f1f5c32c39 100644
--- a/arch/arm64/include/asm/hwcap.h
+++ b/arch/arm64/include/asm/hwcap.h
@@ -31,6 +31,8 @@
#define COMPAT_HWCAP_VFPD32 (1 << 19)
#define COMPAT_HWCAP_LPAE (1 << 20)
#define COMPAT_HWCAP_EVTSTRM (1 << 21)
+#define COMPAT_HWCAP_FPHP (1 << 22)
+#define COMPAT_HWCAP_ASIMDHP (1 << 23)
#define COMPAT_HWCAP2_AES (1 << 0)
#define COMPAT_HWCAP2_PMULL (1 << 1)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 43e5b43ef550..1dc06f086b84 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -442,8 +442,8 @@ static const struct arm64_ftr_bits ftr_mvfr0[] = {
static const struct arm64_ftr_bits ftr_mvfr1[] = {
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDFMAC_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPHP_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDHP_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPHP_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDHP_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDSP_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDINT_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDLS_SHIFT, 4, 0),
@@ -2842,6 +2842,8 @@ static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
/* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
+ HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_FPHP_SHIFT, 4, FTR_UNSIGNED, 3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP),
+ HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDHP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP),
HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index 28d4f442b0bc..c19922a7402d 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -143,6 +143,8 @@ static const char *const compat_hwcap_str[] = {
[COMPAT_KERNEL_HWCAP(VFPD32)] = NULL, /* Not possible on arm64 */
[COMPAT_KERNEL_HWCAP(LPAE)] = "lpae",
[COMPAT_KERNEL_HWCAP(EVTSTRM)] = "evtstrm",
+ [COMPAT_KERNEL_HWCAP(FPHP)] = "fphp",
+ [COMPAT_KERNEL_HWCAP(ASIMDHP)] = "asimdhp",
};
#define COMPAT_KERNEL_HWCAP2(x) const_ilog2(COMPAT_HWCAP2_ ## x)
--
2.17.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 2/8] arm64: Add compat hwcap FPHP and ASIMDHP
2022-10-26 5:58 ` [PATCH 2/8] arm64: Add compat hwcap FPHP and ASIMDHP Amit Daniel Kachhap
@ 2022-11-09 18:00 ` Will Deacon
2022-11-10 4:18 ` Amit Kachhap
0 siblings, 1 reply; 15+ messages in thread
From: Will Deacon @ 2022-11-09 18:00 UTC (permalink / raw)
To: Amit Daniel Kachhap; +Cc: linux-arm-kernel, Catalin Marinas
On Wed, Oct 26, 2022 at 11:28:07AM +0530, Amit Daniel Kachhap wrote:
> These hwcaps are earlier added for 32-bit native arm kernel and hence the
> corresponding changes added in 32-bit compat arm64 kernel for similar
> userspace interface. Floating point half-precision (FPHP) and Advanced
> SIMD half-precision (ASIMDHP) represent the Armv8 FP16 feature extension
> and is already advertised in arm64 kernel.
Can you provide a pointer to the commit adding these for arch/arm/, please?
I've not been able to spot them in linux-next so I'm a bit confused.
Will
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/8] arm64: Add compat hwcap FPHP and ASIMDHP
2022-11-09 18:00 ` Will Deacon
@ 2022-11-10 4:18 ` Amit Kachhap
2022-11-15 15:32 ` Catalin Marinas
0 siblings, 1 reply; 15+ messages in thread
From: Amit Kachhap @ 2022-11-10 4:18 UTC (permalink / raw)
To: Will Deacon; +Cc: linux-arm-kernel, Catalin Marinas
On 11/9/22 23:30, Will Deacon wrote:
> On Wed, Oct 26, 2022 at 11:28:07AM +0530, Amit Daniel Kachhap wrote:
>> These hwcaps are earlier added for 32-bit native arm kernel and hence the
>> corresponding changes added in 32-bit compat arm64 kernel for similar
>> userspace interface. Floating point half-precision (FPHP) and Advanced
>> SIMD half-precision (ASIMDHP) represent the Armv8 FP16 feature extension
>> and is already advertised in arm64 kernel.
>
> Can you provide a pointer to the commit adding these for arch/arm/, please?
> I've not been able to spot them in linux-next so I'm a bit confused.
Those arch/arm/ patches are not merged yet. I only posted in the mailing
list.
Here is the link to it.
http://lists.infradead.org/pipermail/linux-arm-kernel/2022-October/784016.html
Thanks,
Amit
>
> Will
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/8] arm64: Add compat hwcap FPHP and ASIMDHP
2022-11-10 4:18 ` Amit Kachhap
@ 2022-11-15 15:32 ` Catalin Marinas
0 siblings, 0 replies; 15+ messages in thread
From: Catalin Marinas @ 2022-11-15 15:32 UTC (permalink / raw)
To: Amit Kachhap; +Cc: Will Deacon, linux-arm-kernel
On Thu, Nov 10, 2022 at 09:48:59AM +0530, Amit Kachhap wrote:
> On 11/9/22 23:30, Will Deacon wrote:
> > On Wed, Oct 26, 2022 at 11:28:07AM +0530, Amit Daniel Kachhap wrote:
> > > These hwcaps are earlier added for 32-bit native arm kernel and hence the
> > > corresponding changes added in 32-bit compat arm64 kernel for similar
> > > userspace interface. Floating point half-precision (FPHP) and Advanced
> > > SIMD half-precision (ASIMDHP) represent the Armv8 FP16 feature extension
> > > and is already advertised in arm64 kernel.
> >
> > Can you provide a pointer to the commit adding these for arch/arm/, please?
> > I've not been able to spot them in linux-next so I'm a bit confused.
>
> Those arch/arm/ patches are not merged yet. I only posted in the mailing
> list.
> Here is the link to it. http://lists.infradead.org/pipermail/linux-arm-kernel/2022-October/784016.html
We'd need to get the arm32 changes reviewed and merged first before we
can take the arm64 compat counterpart.
--
Catalin
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^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 3/8] arm64: Add compat hwcap ASIMDDP
2022-10-26 5:58 [PATCH 0/8] arm64: Expose compat Armv8 AArch32 features Amit Daniel Kachhap
2022-10-26 5:58 ` [PATCH 1/8] arm64: cpufeature: Fix the visibility of compat hwcaps Amit Daniel Kachhap
2022-10-26 5:58 ` [PATCH 2/8] arm64: Add compat hwcap FPHP and ASIMDHP Amit Daniel Kachhap
@ 2022-10-26 5:58 ` Amit Daniel Kachhap
2022-10-26 5:58 ` [PATCH 4/8] arm64: Add compat hwcap ASIMDFHM Amit Daniel Kachhap
` (4 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Amit Daniel Kachhap @ 2022-10-26 5:58 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Catalin Marinas, Will Deacon, Amit Daniel Kachhap
This hwcap is earlier added for 32-bit native arm kernel and hence the
corresponding changes added in 32-bit compat arm64 also for similar user
interface. Advanced Dot product is a feature (FEAT_DotProd) present in both
AArch32/AArch64 state for Armv8 and is already advertised in arm64 kernel.
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
---
arch/arm64/include/asm/hwcap.h | 1 +
arch/arm64/kernel/cpufeature.c | 3 ++-
arch/arm64/kernel/cpuinfo.c | 1 +
3 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h
index a3f1f5c32c39..cb0d215d776f 100644
--- a/arch/arm64/include/asm/hwcap.h
+++ b/arch/arm64/include/asm/hwcap.h
@@ -33,6 +33,7 @@
#define COMPAT_HWCAP_EVTSTRM (1 << 21)
#define COMPAT_HWCAP_FPHP (1 << 22)
#define COMPAT_HWCAP_ASIMDHP (1 << 23)
+#define COMPAT_HWCAP_ASIMDDP (1 << 24)
#define COMPAT_HWCAP2_AES (1 << 0)
#define COMPAT_HWCAP2_PMULL (1 << 1)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 1dc06f086b84..010eaf96cc3b 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -532,7 +532,7 @@ static const struct arm64_ftr_bits ftr_id_isar6[] = {
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0),
ARM64_FTR_END,
};
@@ -2849,6 +2849,7 @@ static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
+ HWCAP_CAP(SYS_ID_ISAR6_EL1, ID_ISAR6_DP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP),
#endif
{},
};
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index c19922a7402d..5875865c5bfd 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -145,6 +145,7 @@ static const char *const compat_hwcap_str[] = {
[COMPAT_KERNEL_HWCAP(EVTSTRM)] = "evtstrm",
[COMPAT_KERNEL_HWCAP(FPHP)] = "fphp",
[COMPAT_KERNEL_HWCAP(ASIMDHP)] = "asimdhp",
+ [COMPAT_KERNEL_HWCAP(ASIMDDP)] = "asimddp",
};
#define COMPAT_KERNEL_HWCAP2(x) const_ilog2(COMPAT_HWCAP2_ ## x)
--
2.17.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 4/8] arm64: Add compat hwcap ASIMDFHM
2022-10-26 5:58 [PATCH 0/8] arm64: Expose compat Armv8 AArch32 features Amit Daniel Kachhap
` (2 preceding siblings ...)
2022-10-26 5:58 ` [PATCH 3/8] arm64: Add compat hwcap ASIMDDP Amit Daniel Kachhap
@ 2022-10-26 5:58 ` Amit Daniel Kachhap
2022-10-26 5:58 ` [PATCH 5/8] arm64: Add compat hwcap ASIMDBF16 Amit Daniel Kachhap
` (3 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Amit Daniel Kachhap @ 2022-10-26 5:58 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Catalin Marinas, Will Deacon, Amit Daniel Kachhap
This hwcap is earlier added for 32-bit native arm kernel and hence the
corresponding changes added in 32-bit compat arm64 also for similar user
interface. Floating-point half-precision multiplication (FHM) is a feature
present in AArch32/AArch64 state for Armv8 and is identified by ISAR6.FHM
identification register. This hwcap is already advertised in arm64 kernel.
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
---
arch/arm64/include/asm/hwcap.h | 1 +
arch/arm64/kernel/cpufeature.c | 3 ++-
arch/arm64/kernel/cpuinfo.c | 1 +
3 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h
index cb0d215d776f..8d944397a9a3 100644
--- a/arch/arm64/include/asm/hwcap.h
+++ b/arch/arm64/include/asm/hwcap.h
@@ -34,6 +34,7 @@
#define COMPAT_HWCAP_FPHP (1 << 22)
#define COMPAT_HWCAP_ASIMDHP (1 << 23)
#define COMPAT_HWCAP_ASIMDDP (1 << 24)
+#define COMPAT_HWCAP_ASIMDFHM (1 << 25)
#define COMPAT_HWCAP2_AES (1 << 0)
#define COMPAT_HWCAP2_PMULL (1 << 1)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 010eaf96cc3b..8b6d0ed571ce 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -531,7 +531,7 @@ static const struct arm64_ftr_bits ftr_id_isar6[] = {
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0),
ARM64_FTR_END,
@@ -2850,6 +2850,7 @@ static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
HWCAP_CAP(SYS_ID_ISAR6_EL1, ID_ISAR6_DP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP),
+ HWCAP_CAP(SYS_ID_ISAR6_EL1, ID_ISAR6_FHM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM),
#endif
{},
};
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index 5875865c5bfd..23afcd80c7fd 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -146,6 +146,7 @@ static const char *const compat_hwcap_str[] = {
[COMPAT_KERNEL_HWCAP(FPHP)] = "fphp",
[COMPAT_KERNEL_HWCAP(ASIMDHP)] = "asimdhp",
[COMPAT_KERNEL_HWCAP(ASIMDDP)] = "asimddp",
+ [COMPAT_KERNEL_HWCAP(ASIMDFHM)] = "asimdfhm",
};
#define COMPAT_KERNEL_HWCAP2(x) const_ilog2(COMPAT_HWCAP2_ ## x)
--
2.17.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 5/8] arm64: Add compat hwcap ASIMDBF16
2022-10-26 5:58 [PATCH 0/8] arm64: Expose compat Armv8 AArch32 features Amit Daniel Kachhap
` (3 preceding siblings ...)
2022-10-26 5:58 ` [PATCH 4/8] arm64: Add compat hwcap ASIMDFHM Amit Daniel Kachhap
@ 2022-10-26 5:58 ` Amit Daniel Kachhap
2022-10-26 5:58 ` [PATCH 6/8] arm64: Add compat hwcap I8MM Amit Daniel Kachhap
` (2 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Amit Daniel Kachhap @ 2022-10-26 5:58 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Catalin Marinas, Will Deacon, Amit Daniel Kachhap
This hwcap is earlier added for 32-bit native arm kernel and hence the
corresponding changes added in 32-bit compat arm64 kernel.
Brain 16-bit floating-point storage format is a feature (FEAT_AA32BF16)
present in AArch32 state for Armv8 and is represented by ISAR6.BF16
identification register. Similar feature (FEAT_BF16) exist for AArch64
state and is already advertised in arm64 kernel.
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
---
arch/arm64/include/asm/hwcap.h | 1 +
arch/arm64/kernel/cpufeature.c | 3 ++-
arch/arm64/kernel/cpuinfo.c | 1 +
3 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h
index 8d944397a9a3..62e7eadecb30 100644
--- a/arch/arm64/include/asm/hwcap.h
+++ b/arch/arm64/include/asm/hwcap.h
@@ -35,6 +35,7 @@
#define COMPAT_HWCAP_ASIMDHP (1 << 23)
#define COMPAT_HWCAP_ASIMDDP (1 << 24)
#define COMPAT_HWCAP_ASIMDFHM (1 << 25)
+#define COMPAT_HWCAP_ASIMDBF16 (1 << 26)
#define COMPAT_HWCAP2_AES (1 << 0)
#define COMPAT_HWCAP2_PMULL (1 << 1)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 8b6d0ed571ce..213f41cb477b 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -528,7 +528,7 @@ static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
static const struct arm64_ftr_bits ftr_id_isar6[] = {
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),
@@ -2851,6 +2851,7 @@ static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
HWCAP_CAP(SYS_ID_ISAR6_EL1, ID_ISAR6_DP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP),
HWCAP_CAP(SYS_ID_ISAR6_EL1, ID_ISAR6_FHM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM),
+ HWCAP_CAP(SYS_ID_ISAR6_EL1, ID_ISAR6_BF16_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16),
#endif
{},
};
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index 23afcd80c7fd..a76e66947bcb 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -147,6 +147,7 @@ static const char *const compat_hwcap_str[] = {
[COMPAT_KERNEL_HWCAP(ASIMDHP)] = "asimdhp",
[COMPAT_KERNEL_HWCAP(ASIMDDP)] = "asimddp",
[COMPAT_KERNEL_HWCAP(ASIMDFHM)] = "asimdfhm",
+ [COMPAT_KERNEL_HWCAP(ASIMDBF16)] = "asimdbf16",
};
#define COMPAT_KERNEL_HWCAP2(x) const_ilog2(COMPAT_HWCAP2_ ## x)
--
2.17.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 6/8] arm64: Add compat hwcap I8MM
2022-10-26 5:58 [PATCH 0/8] arm64: Expose compat Armv8 AArch32 features Amit Daniel Kachhap
` (4 preceding siblings ...)
2022-10-26 5:58 ` [PATCH 5/8] arm64: Add compat hwcap ASIMDBF16 Amit Daniel Kachhap
@ 2022-10-26 5:58 ` Amit Daniel Kachhap
2022-10-26 5:58 ` [PATCH 7/8] arm64: Add compat hwcap SB Amit Daniel Kachhap
2022-10-26 5:58 ` [PATCH 8/8] arm64: Add compat hwcap SSBS Amit Daniel Kachhap
7 siblings, 0 replies; 15+ messages in thread
From: Amit Daniel Kachhap @ 2022-10-26 5:58 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Catalin Marinas, Will Deacon, Amit Daniel Kachhap
This hwcap is added earlier for 32-bit native arm kernel and hence the
corresponding changes added in 32-bit compat arm64 kernel for similar
user interface. Int8 matrix multiplication is a feature (FEAT_AA32I8MM)
present in AArch32 state of Armv8 and is identified by ISAR6.I8MM register.
Similar feature (FEAT_I8MM) exist for AArch64 state and is already
advertised in arm64 kernel.
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
---
arch/arm64/include/asm/hwcap.h | 1 +
arch/arm64/kernel/cpufeature.c | 3 ++-
arch/arm64/kernel/cpuinfo.c | 1 +
3 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h
index 62e7eadecb30..d2ef58f95b48 100644
--- a/arch/arm64/include/asm/hwcap.h
+++ b/arch/arm64/include/asm/hwcap.h
@@ -36,6 +36,7 @@
#define COMPAT_HWCAP_ASIMDDP (1 << 24)
#define COMPAT_HWCAP_ASIMDFHM (1 << 25)
#define COMPAT_HWCAP_ASIMDBF16 (1 << 26)
+#define COMPAT_HWCAP_I8MM (1 << 27)
#define COMPAT_HWCAP2_AES (1 << 0)
#define COMPAT_HWCAP2_PMULL (1 << 1)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 213f41cb477b..b17c4de13e01 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -527,7 +527,7 @@ static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
};
static const struct arm64_ftr_bits ftr_id_isar6[] = {
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),
@@ -2852,6 +2852,7 @@ static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
HWCAP_CAP(SYS_ID_ISAR6_EL1, ID_ISAR6_DP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP),
HWCAP_CAP(SYS_ID_ISAR6_EL1, ID_ISAR6_FHM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM),
HWCAP_CAP(SYS_ID_ISAR6_EL1, ID_ISAR6_BF16_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16),
+ HWCAP_CAP(SYS_ID_ISAR6_EL1, ID_ISAR6_I8MM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM),
#endif
{},
};
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index a76e66947bcb..4cb3f089f1ad 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -148,6 +148,7 @@ static const char *const compat_hwcap_str[] = {
[COMPAT_KERNEL_HWCAP(ASIMDDP)] = "asimddp",
[COMPAT_KERNEL_HWCAP(ASIMDFHM)] = "asimdfhm",
[COMPAT_KERNEL_HWCAP(ASIMDBF16)] = "asimdbf16",
+ [COMPAT_KERNEL_HWCAP(I8MM)] = "i8mm",
};
#define COMPAT_KERNEL_HWCAP2(x) const_ilog2(COMPAT_HWCAP2_ ## x)
--
2.17.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 7/8] arm64: Add compat hwcap SB
2022-10-26 5:58 [PATCH 0/8] arm64: Expose compat Armv8 AArch32 features Amit Daniel Kachhap
` (5 preceding siblings ...)
2022-10-26 5:58 ` [PATCH 6/8] arm64: Add compat hwcap I8MM Amit Daniel Kachhap
@ 2022-10-26 5:58 ` Amit Daniel Kachhap
2022-10-26 5:58 ` [PATCH 8/8] arm64: Add compat hwcap SSBS Amit Daniel Kachhap
7 siblings, 0 replies; 15+ messages in thread
From: Amit Daniel Kachhap @ 2022-10-26 5:58 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Catalin Marinas, Will Deacon, Amit Daniel Kachhap
This hwcap is added earlier for 32-bit native arm kernel and hence the
corresponding changes added in 32-bit compat arm64 kernel. Speculation
Barrier is a feature(FEAT_SB) present in both AArch32 and AArch64 state
and can be identified by ISAR6.SB register. This hwcap is already
advertised in arm64 kernel.
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
---
arch/arm64/include/asm/hwcap.h | 1 +
arch/arm64/kernel/cpufeature.c | 3 ++-
arch/arm64/kernel/cpuinfo.c | 1 +
3 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h
index d2ef58f95b48..adfc6be14c53 100644
--- a/arch/arm64/include/asm/hwcap.h
+++ b/arch/arm64/include/asm/hwcap.h
@@ -43,6 +43,7 @@
#define COMPAT_HWCAP2_SHA1 (1 << 2)
#define COMPAT_HWCAP2_SHA2 (1 << 3)
#define COMPAT_HWCAP2_CRC32 (1 << 4)
+#define COMPAT_HWCAP2_SB (1 << 5)
#ifndef __ASSEMBLY__
#include <linux/log2.h>
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index b17c4de13e01..9bc58c3661f4 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -530,7 +530,7 @@ static const struct arm64_ftr_bits ftr_id_isar6[] = {
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0),
@@ -2851,6 +2851,7 @@ static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
HWCAP_CAP(SYS_ID_ISAR6_EL1, ID_ISAR6_DP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP),
HWCAP_CAP(SYS_ID_ISAR6_EL1, ID_ISAR6_FHM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM),
+ HWCAP_CAP(SYS_ID_ISAR6_EL1, ID_ISAR6_SB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB),
HWCAP_CAP(SYS_ID_ISAR6_EL1, ID_ISAR6_BF16_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16),
HWCAP_CAP(SYS_ID_ISAR6_EL1, ID_ISAR6_I8MM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM),
#endif
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index 4cb3f089f1ad..afbceb5b2bab 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -158,6 +158,7 @@ static const char *const compat_hwcap2_str[] = {
[COMPAT_KERNEL_HWCAP2(SHA1)] = "sha1",
[COMPAT_KERNEL_HWCAP2(SHA2)] = "sha2",
[COMPAT_KERNEL_HWCAP2(CRC32)] = "crc32",
+ [COMPAT_KERNEL_HWCAP2(SB)] = "sb",
};
#endif /* CONFIG_COMPAT */
--
2.17.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 8/8] arm64: Add compat hwcap SSBS
2022-10-26 5:58 [PATCH 0/8] arm64: Expose compat Armv8 AArch32 features Amit Daniel Kachhap
` (6 preceding siblings ...)
2022-10-26 5:58 ` [PATCH 7/8] arm64: Add compat hwcap SB Amit Daniel Kachhap
@ 2022-10-26 5:58 ` Amit Daniel Kachhap
7 siblings, 0 replies; 15+ messages in thread
From: Amit Daniel Kachhap @ 2022-10-26 5:58 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Catalin Marinas, Will Deacon, Amit Daniel Kachhap
This hwcap is added earlier for 32-bit native arm kernel and hence the
corresponding changes added in 32-bit compat arm64 for similar user
interface. Speculative Store Bypass Safe is a feature(FEAT_SSBS) present in
AArch32/AArch64 state for Armv8 and can be identified by PFR2.SSBS
identification register. This hwcap is already advertised in arm64 kernel.
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
---
arch/arm64/include/asm/hwcap.h | 1 +
arch/arm64/kernel/cpufeature.c | 3 ++-
arch/arm64/kernel/cpuinfo.c | 1 +
3 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h
index adfc6be14c53..e7c3dd8f71e0 100644
--- a/arch/arm64/include/asm/hwcap.h
+++ b/arch/arm64/include/asm/hwcap.h
@@ -44,6 +44,7 @@
#define COMPAT_HWCAP2_SHA2 (1 << 3)
#define COMPAT_HWCAP2_CRC32 (1 << 4)
#define COMPAT_HWCAP2_SB (1 << 5)
+#define COMPAT_HWCAP2_SSBS (1 << 6)
#ifndef __ASSEMBLY__
#include <linux/log2.h>
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 9bc58c3661f4..56e5ab35e942 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -560,7 +560,7 @@ static const struct arm64_ftr_bits ftr_id_pfr1[] = {
};
static const struct arm64_ftr_bits ftr_id_pfr2[] = {
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0),
ARM64_FTR_END,
};
@@ -2854,6 +2854,7 @@ static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
HWCAP_CAP(SYS_ID_ISAR6_EL1, ID_ISAR6_SB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB),
HWCAP_CAP(SYS_ID_ISAR6_EL1, ID_ISAR6_BF16_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16),
HWCAP_CAP(SYS_ID_ISAR6_EL1, ID_ISAR6_I8MM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM),
+ HWCAP_CAP(SYS_ID_PFR2_EL1, ID_PFR2_SSBS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS),
#endif
{},
};
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index afbceb5b2bab..c49582d1372f 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -159,6 +159,7 @@ static const char *const compat_hwcap2_str[] = {
[COMPAT_KERNEL_HWCAP2(SHA2)] = "sha2",
[COMPAT_KERNEL_HWCAP2(CRC32)] = "crc32",
[COMPAT_KERNEL_HWCAP2(SB)] = "sb",
+ [COMPAT_KERNEL_HWCAP2(SSBS)] = "ssbs",
};
#endif /* CONFIG_COMPAT */
--
2.17.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread