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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id q21-20020a056830233500b00661c0747545sm5655710otg.44.2022.11.02.14.44.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Nov 2022 14:44:54 -0700 (PDT) Received: (nullmailer pid 522290 invoked by uid 1000); Wed, 02 Nov 2022 21:44:56 -0000 Date: Wed, 2 Nov 2022 16:44:56 -0500 From: Rob Herring To: Andreas =?iso-8859-1?Q?F=E4rber?= Cc: Chester Lin , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Krzysztof Kozlowski , Jan Petrous , netdev@vger.kernel.org, s32@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Matthias Brugger Subject: Re: [PATCH 2/5] dt-bindings: net: add schema for NXP S32CC dwmac glue driver Message-ID: <20221102214456.GB459441-robh@kernel.org> References: <20221031101052.14956-1-clin@suse.com> <20221031101052.14956-3-clin@suse.com> <20221102155515.GA3959603-robh@kernel.org> <2a7ebef4-77cc-1c26-ec6d-86db5ee5a94b@suse.de> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <2a7ebef4-77cc-1c26-ec6d-86db5ee5a94b@suse.de> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221102_144458_658315_61E6CF7A X-CRM114-Status: GOOD ( 32.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Nov 02, 2022 at 06:13:35PM +0100, Andreas F=E4rber wrote: > Hi Rob, > = > On 02.11.22 16:55, Rob Herring wrote: > > On Mon, Oct 31, 2022 at 06:10:49PM +0800, Chester Lin wrote: > > > Add the DT schema for the DWMAC Ethernet controller on NXP S32 Common > > > Chassis. > > > = > > > Signed-off-by: Jan Petrous > > > Signed-off-by: Chester Lin > > > --- > > > .../bindings/net/nxp,s32cc-dwmac.yaml | 145 +++++++++++++++= +++ > > > 1 file changed, 145 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/net/nxp,s32cc-= dwmac.yaml > > > = > > > diff --git a/Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.ya= ml b/Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml > > > new file mode 100644 > > > index 000000000000..f6b8486f9d42 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml > > > @@ -0,0 +1,145 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > +# Copyright 2021-2022 NXP > > > +%YAML 1.2 > > > +--- > > > +$id: "http://devicetree.org/schemas/net/nxp,s32cc-dwmac.yaml#" > > > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > > > + > > > +title: NXP S32CC DWMAC Ethernet controller > > > + > > > +maintainers: > > > + - Jan Petrous > > > + - Chester Lin > [...] > > > +properties: > > > + compatible: > > > + contains: > > = > > Drop 'contains'. > > = > > > + enum: > > > + - nxp,s32cc-dwmac > = > In the past you were adamant that we use concrete SoC-specific strings. H= ere > that would mean s32g2 or s32g274 instead of s32cc (which aims to share wi= th > S32G3 IIUC). Yes they should be SoC specific. Really, 1 per maskset or die is fine if = that level of detail is known. No need for different compatibles for = different part numbers created by fused off features or package pinout = differences. > [...] > > > + clocks: > > > + items: > > > + - description: Main GMAC clock > > > + - description: Peripheral registers clock > > > + - description: Transmit SGMII clock > > > + - description: Transmit RGMII clock > > > + - description: Transmit RMII clock > > > + - description: Transmit MII clock > > > + - description: Receive SGMII clock > > > + - description: Receive RGMII clock > > > + - description: Receive RMII clock > > > + - description: Receive MII clock > > > + - description: > > > + PTP reference clock. This clock is used for programming the > > > + Timestamp Addend Register. If not passed then the system > > > + clock will be used. > > = > > If optional, then you need 'minItems'. > [snip] > = > Do we have any precedence of bindings with *MII clocks like these? Don't know... > AFAIU the reason there are so many here is that there are in fact physica= lly > just five, but different parent clock configurations that SCMI does not > currently expose to Linux. Thus I was raising that we may want to extend = the > SCMI protocol with some SET_PARENT operation that could allow us to use l= ess > input clocks here, but obviously such a standardization process will take > time... > = > What are your thoughts on how to best handle this here? Perhaps use assigned-clocks if it is static for a board. > Not clear to me has been whether the PHY mode can be switched at runtime > (like DPAA2 on Layerscape allows for SFPs) or whether this is fixed by bo= ard > design. If the latter, the two out of six SCMI IDs could get selected in > TF-A, to have only physical clocks here in the binding. > = > Regards, > Andreas _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel