From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 12401C4332F for ; Fri, 4 Nov 2022 23:56:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=EnOXBJO7RT3kAAXfjPyhPfi2LVJ3rI7v/eMkF4f2Hmw=; b=GjedpteBkv0fVd 3OcvBgnKa42KDB1tRqNQr6Yz4n+8Yno+Cf9wMrTwDrTfIN2G0gW0zwfD9Sjnq4ZVYCp2/7FbduiCP WEunPxtZEGLkKFQLp3Lq0OLcC6sa6p/Qk4C3ty8/0ziQXoDOplSuw7IvdM2SwmEFGmEk9Nel4d52c IOD3b0jriHervS88aLjpMSkU37fm/rVNeXlqBIyQf1n0sCIagE6LCpIATsPKgA2G0Cb+TLoi8dNp1 Dkh/B4GeKdvtyLVJYaG5cKiLk+e4xgHSA4HNItcPts/QJGSisNNEkTF71pVyRpPtOWTn2g+dVgB3H O/k+3cf65ALN6EjGabrw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1or6Wg-005WcM-Tn; Fri, 04 Nov 2022 23:55:07 +0000 Received: from ams.source.kernel.org ([145.40.68.75]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1or6We-005Wbn-3e for linux-arm-kernel@lists.infradead.org; Fri, 04 Nov 2022 23:55:05 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 66B2BB821EA; Fri, 4 Nov 2022 23:55:02 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 18B4EC433D6; Fri, 4 Nov 2022 23:54:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1667606101; bh=DLbJji70wWdrQJY3qY+hujEiXQhpXE5XkslDMnc1+zI=; h=From:To:Cc:Subject:Date:From; b=hHchEMrE7cgpzcvGQvXrz49tqDxsbMfbnaSK/Mg9jXn3Mw+/DW/PBZcs0Zg/Rtk56 yxzFGIVC/xSyfj0Klzr2IAl7yD8UGGOpdxjHCMLNixUuLW7XXEzNJRf0MW31GYVBiH V0wkG8Xl/firZPhXwr1ibekPemg2P8+qayy6mzGrG19dfOZInxGrvvQnJkNz/nvqkd fhPs30RwoggfMUQgWpC8XAh7XUYI7vieclklH+f9Chagdw8dI8M4KBc43U1p2kJAyQ TPa5R0FC+UWWnelPqm1TPpn2D7KwjNY/PwkAcKguvPIRj3ZSMYlcaQ7Nd6dwtYmysP 6FGhao/XTMgTA== From: Mark Brown To: Catalin Marinas , Will Deacon , Marc Zyngier Cc: Lorenzo Pieralisi , Mark Rutland , Sami Mujawar , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v1 00/18] arm64/nmi: Support for FEAT_NMI Date: Fri, 4 Nov 2022 23:54:35 +0000 Message-Id: <20221104235453.870573-1-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4638; i=broonie@kernel.org; h=from:subject; bh=DLbJji70wWdrQJY3qY+hujEiXQhpXE5XkslDMnc1+zI=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBjZaY7GN4FbhYLFWRdvXoi1XaC/tS/hrFxO7m2pW9q pZtiPU6JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCY2WmOwAKCRAk1otyXVSH0IqfB/ 9YTIOumxHsDnMphDUKmn4sFwuppt56OAOo1Pkjv81CNFEtdw77L8+WerdVi50zrr73ffG0I1XgimwJ Gj3tRRhaK+qtdJKjE5B1cGLm1ATJyd75IbfYkX6IBeHnio9j8xG8B+oIfNM1/wk3gjSjBXEnPwWkrR C4jw4Px3Qhs66R5UF6CebSTIuuorvnv3lrk7Cx+YgDa6xKpmc5TBpRrCWYJNgpdq2gkocRHHBBti02 +VA1hDzTO5PBsFZVMEXzqh99y2JTDknCJJr39jlm1W+k3bw/2W6lI2Ru+D1qGgJAA8PoUwSk50ppK4 xXjC3KKXq0/cRQ7J75Ux10TT/dONdL X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221104_165504_469284_3EB6BA13 X-CRM114-Status: GOOD ( 24.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series enables the architecture and GIC support for the arm64 FEAT_NMI and FEAT_GICv3_NMI extensions in host kernels. These introduce support for a new category of interrupts in the architecture code which we can use to provide NMI functionality, though the interrupts are in fact maskable as the name would not imply. The GIC support was done by Loreozo Pieralisi. There are two modes for using this FEAT_NMI, the one we use is the one where any entry to ELn causes all interrupts including those with superpriority to be masked by a new mask bit ALLINT.ALLINT on entry to ELn until the mask is explicitly removed by software. We do this early in the C entry code for anything that is not a superpriority interrupt, those are handled without unmasking. Independent controls are provided for this feature at each EL, usage at EL1 should not disrupt EL2 or EL3. Since we can mask these not quite NMIs a large portion of the series is concerned with updating places where we really do not want to be taking interrupts of any kind to add masking for NMIs. This masking is not added to our standard interrupt masking operations since that would result in widespread masking of NMIs which would undermine their value. Given that there's a large amount of kernel code a good proportion of which I'm not terribly familar with it is likely that this area of the series needs attention in review as there may be be be areas that have been missed or misunderstood. In order to ensure that we do not have both pseudo NMIs and real NMIs simultaneously enabled we disable NMIs if pseudo NMI support is enabled in the kernel and has been requested on the command line, since pseudo NMIs require explicit enablement it seemed most sensible to trust that the user preferred them for some reason. Using this feature in KVM guests will require the implementation of vGIC support which is not present in this series, and there is also no usage of the feature at EL2. While FEAT_NMI does add a new writable register ALLINT the value is already context switched for EL1 via SPSR_EL2.ALLINT and we can't trap read access to the register so we don't manage the write trap that is available in HCRX_EL2.TALLINT. Guests can read from the register anyway and should only be able to affect their own state. Lorenzo Pieralisi (1): irqchip/gic-v3: Implement FEAT_GICv3_NMI support Mark Brown (17): arm64/booting: Document boot requirements for FEAT_NMI arm64/sysreg: Add definition for ICC_NMIAR1_EL1 arm64/sysreg: Add definition of ISR_EL1 arm64/sysreg: Add definitions for immediate versions of MSR ALLINT arm64/asm: Introduce assembly macros for managing ALLINT arm64/hyp-stub: Enable access to ALLINT arm64/idreg: Add an override for FEAT_NMI arm64/cpufeature: Detect PE support for NMIs arm64/entry: Manage ALLINT.ALLINT when FEAT_NMI is active arm64/mm: Disable all interrupts while replacing TTBR1 arm64/hibernate: Disable NMIs while hibernating arm64/suspend: Disable NMIs while suspending arm64/kexec: Mask NMIs before starting new kernel arm64/acpi: Mask NMIs while notifying SEA arm64/irq: Document handling of FEAT_NMI in irqflags.h arm64/nmi: Add handling of superpriority interrupts as NMIs arm64/nmi: Add Kconfig for NMI Documentation/arm64/booting.rst | 6 ++ arch/arm64/Kconfig | 17 ++++ arch/arm64/include/asm/assembler.h | 16 ++++ arch/arm64/include/asm/cpufeature.h | 6 ++ arch/arm64/include/asm/daifflags.h | 1 + arch/arm64/include/asm/irq.h | 2 + arch/arm64/include/asm/irqflags.h | 10 ++ arch/arm64/include/asm/nmi.h | 30 ++++++ arch/arm64/include/asm/sysreg.h | 2 + arch/arm64/kernel/acpi.c | 8 +- arch/arm64/kernel/cpufeature.c | 55 ++++++++++- arch/arm64/kernel/entry-common.c | 73 ++++++++++++-- arch/arm64/kernel/hibernate.c | 12 +++ arch/arm64/kernel/hyp-stub.S | 12 +++ arch/arm64/kernel/idreg-override.c | 1 + arch/arm64/kernel/irq.c | 32 +++++++ arch/arm64/kernel/machine_kexec.c | 2 + arch/arm64/kernel/suspend.c | 11 +++ arch/arm64/mm/proc.S | 2 + arch/arm64/tools/cpucaps | 1 + arch/arm64/tools/sysreg | 15 +++ drivers/irqchip/irq-gic-v3.c | 143 +++++++++++++++++++++++----- include/linux/irqchip/arm-gic-v3.h | 4 + 23 files changed, 428 insertions(+), 33 deletions(-) create mode 100644 arch/arm64/include/asm/nmi.h base-commit: 30a0b95b1335e12efef89dd78518ed3e4a71a763 -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel