From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3C53DC433FE for ; Fri, 4 Nov 2022 23:57:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=/N0owAC2LvSo14IfKPuek2pBhJ0Zsn/MEOzWdMagXNY=; b=KD/Rr02dnTpHlW /LYE7VxeX1QJDidPf3y75oqiPbOUpEn2RG+y0M8/mAGcEQabSAfHM3o44/bARJonLrY2n1OxhuC6m BzthYTW7d6MEMNCb/c8KXD4PCsxHfJeOmw81hBjFHrxZ7v/F4e4r/E+IL0OXRQj4BVbiyRAAt1QAX +nA7cYSfprspTiKGMBT6v4k0zUgx9U5eSOff5DKE0nWgvK53o/QVjc/P/NUhidMQeczZwPFp3dj3D jygZMgtS/fA85vMhVQ+yJIdDwq+056YSgHDVmuC3SRgtuDkbcEvq9QlfZ92/Nh62YWAOVAktAEmgC WvP6BSFtjmsHAnnVV+/Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1or6YH-005XLL-HO; Fri, 04 Nov 2022 23:56:45 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1or6Wv-005Wfu-Gx for linux-arm-kernel@lists.infradead.org; Fri, 04 Nov 2022 23:55:23 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id B3D8362391; Fri, 4 Nov 2022 23:55:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 33072C433D6; Fri, 4 Nov 2022 23:55:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1667606120; bh=roolAkbnZmev2vrGcjgD0hJYeDdlkHxjYXoV5iFIhl8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lamIq34/RVR2Y8xbKJj7jKPsBeTL+iGHpHq2gLdrgjISVO3liK64Hz35nl37St2aQ c5DZa/oEGU86B1IwPmk33T+YyROoG8z6pkYLCYOacfqtJa0kuTtpBH8RbePG/XYnB6 EtjxIOPv3qCESPvfILTdcVd3TK6u9RAAGJkl3e5eBONV6NCVXTqizVcg1I4JYv3Ic3 c+uUDYrEgaQzJ8NhFOqCZPqxr8iDAmjuXdcciylXvalja20Ej2Zntm57i6WXR8Cg4V hjXSfTsYtfa/ZAyy14Cp6tKtkfc0zs7oxFMQ+AoRLfzGzdmZCkayzFF/MPSpISmchE yU0OoG0LNc1JA== From: Mark Brown To: Catalin Marinas , Will Deacon , Marc Zyngier Cc: Lorenzo Pieralisi , Mark Rutland , Sami Mujawar , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v1 08/18] arm64/cpufeature: Detect PE support for NMIs Date: Fri, 4 Nov 2022 23:54:43 +0000 Message-Id: <20221104235453.870573-9-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221104235453.870573-1-broonie@kernel.org> References: <20221104235453.870573-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5639; i=broonie@kernel.org; h=from:subject; bh=roolAkbnZmev2vrGcjgD0hJYeDdlkHxjYXoV5iFIhl8=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBjZaZCZActrAyo0CEnFD4YOwYK2Z0mLmiwPzpqGfq8 eyDTZ6SJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCY2WmQgAKCRAk1otyXVSH0JGZB/ wIdeCHeYdBVPVExSoXSAnzP5AN8meKjbwUcpT2HUqUXaDmMoFkTqdut+cGNsWp/JxuILaIRN8S0ieX 7o4gK31HweSuknmAkCSmn8HfXdgXhp6AtRf0vJ8Xkm7kskUL/1tqXIqbSysuhl5Z2QIiQEje4xI8iO MUUfrdtZJJKCoaiGLzilTMyPXpg7m6m8eQC4Sd8ff2U6/Vq8K9VZ4ZUsFd+gRUEKX/77JiCZDsaWSW 7glX1y6sNnOKmSBw+UPIe0HK+UjpP+Mt//tNYSKi5YuuAgbYNiYlRpBw2dz+9G/BzhXH9DnU0MVrEb feKCu8dSlfbCT4mYUwE+8W8d74faGR X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221104_165521_661125_1F1CBB9D X-CRM114-Status: GOOD ( 22.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Use of NMIs requires that all the PEs in the system and the GIC have NMI support. This patch implements the PE part of that detection and adds wrapped mask/unmask functions with feature detection in them. In order to avoid problematic interactions between real and pseudo NMIs we disable the architected NMIs if the user has enabled pseudo NMIs on the command line. If this is done on a system where support for the architected NMIs is detected then a warning is printed during boot in order to help users spot what is likely to be a misconfiguration. Signed-off-by: Mark Brown --- arch/arm64/include/asm/cpufeature.h | 6 ++++ arch/arm64/include/asm/nmi.h | 12 +++++++ arch/arm64/kernel/cpufeature.c | 55 ++++++++++++++++++++++++++++- arch/arm64/tools/cpucaps | 1 + 4 files changed, 73 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index f73f11b55042..85eeb331a0ef 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -809,6 +809,12 @@ static __always_inline bool system_uses_irq_prio_masking(void) cpus_have_const_cap(ARM64_HAS_IRQ_PRIO_MASKING); } +static __always_inline bool system_uses_nmi(void) +{ + return IS_ENABLED(CONFIG_ARM64_NMI) && + cpus_have_const_cap(ARM64_HAS_NMI); +} + static inline bool system_supports_mte(void) { return IS_ENABLED(CONFIG_ARM64_MTE) && diff --git a/arch/arm64/include/asm/nmi.h b/arch/arm64/include/asm/nmi.h index 067e2554e144..408af57e23dc 100644 --- a/arch/arm64/include/asm/nmi.h +++ b/arch/arm64/include/asm/nmi.h @@ -10,9 +10,21 @@ static __always_inline void _allint_clear(void) asm volatile(__msr_s(SYS_ALLINT_CLR, "xzr")); } +static __always_inline void nmi_unmask(void) +{ + if (system_uses_nmi()) + _allint_clear(); +} + static __always_inline void _allint_set(void) { asm volatile(__msr_s(SYS_ALLINT_SET, "xzr")); } +static __always_inline void nmi_mask(void) +{ + if (system_uses_nmi()) + _allint_set(); +} + #endif diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 6062454a9067..18ab50b76f50 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -84,6 +84,7 @@ #include #include #include +#include #include #include #include @@ -243,6 +244,7 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { }; static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_NMI_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), @@ -2008,9 +2010,11 @@ static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) } #endif /* CONFIG_ARM64_E0PD */ -#ifdef CONFIG_ARM64_PSEUDO_NMI +#if IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) || IS_ENABLED(CONFIG_ARM64_NMI) static bool enable_pseudo_nmi; +#endif +#ifdef CONFIG_ARM64_PSEUDO_NMI static int __init early_enable_pseudo_nmi(char *p) { return strtobool(p, &enable_pseudo_nmi); @@ -2024,6 +2028,41 @@ static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, } #endif +#ifdef CONFIG_ARM64_NMI +static bool has_nmi(const struct arm64_cpu_capabilities *entry, int scope) +{ + if (!has_cpuid_feature(entry, scope)) + return false; + + /* + * Having both real and pseudo NMIs enabled simultaneously is + * likely to cause confusion. Since pseudo NMIs must be + * enabled with an explicit command line option, if the user + * has set that option on a system with real NMIs for some + * reason assume they know what they're doing. + */ + if (IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && enable_pseudo_nmi) { + pr_info("Pseudo NMI enabled, not using architected NMI\n"); + return false; + } + + return true; +} + +static void nmi_enable(const struct arm64_cpu_capabilities *__unused) +{ + /* + * Enable use of NMIs controlled by ALLINT, SPINTMASK should + * be clear by default but make it explicit that we are using + * this mode. Ensure that ALLINT is clear first in order to + * avoid leaving things masked. + */ + _allint_clear(); + sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPINTMASK, SCTLR_EL1_NMI); + isb(); +} +#endif + #ifdef CONFIG_ARM64_BTI static void bti_enable(const struct arm64_cpu_capabilities *__unused) { @@ -2640,6 +2679,20 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = has_cpuid_feature, .cpu_enable = cpu_trap_el0_impdef, }, +#ifdef CONFIG_ARM64_NMI + { + .desc = "Non-maskable Interrupts", + .capability = ARM64_HAS_NMI, + .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, + .sys_reg = SYS_ID_AA64PFR1_EL1, + .sign = FTR_UNSIGNED, + .field_pos = ID_AA64PFR1_EL1_NMI_SHIFT, + .field_width = 4, + .min_field_value = ID_AA64PFR1_EL1_NMI_IMP, + .matches = has_nmi, + .cpu_enable = nmi_enable, + }, +#endif {}, }; diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index f1c0347ec31a..fff7517ea590 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -30,6 +30,7 @@ HAS_GENERIC_AUTH_IMP_DEF HAS_IRQ_PRIO_MASKING HAS_LDAPR HAS_LSE_ATOMICS +HAS_NMI HAS_NO_FPSIMD HAS_NO_HW_PREFETCH HAS_PAN -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel