From: Marc Zyngier <maz@kernel.org>
To: linux-arm-kernel@lists.infradead.org,
<kvmarm@lists.cs.columbia.edu>, <kvmarm@lists.linux.dev>,
kvm@vger.kernel.org
Cc: James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
Ricardo Koller <ricarkol@google.com>,
Reiji Watanabe <reijiw@google.com>
Subject: [PATCH v3 06/14] KVM: arm64: PMU: Only narrow counters that are not 64bit wide
Date: Mon, 7 Nov 2022 08:54:27 +0000 [thread overview]
Message-ID: <20221107085435.2581641-7-maz@kernel.org> (raw)
In-Reply-To: <20221107085435.2581641-1-maz@kernel.org>
The current PMU emulation sometimes narrows counters to 32bit
if the counter isn't the cycle counter. As this is going to
change with PMUv3p5 where the counters are all 64bit, fix
the couple of cases where this happens unconditionally.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/kvm/pmu-emul.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
index 39a04ae424d1..8f6462cbc408 100644
--- a/arch/arm64/kvm/pmu-emul.c
+++ b/arch/arm64/kvm/pmu-emul.c
@@ -151,20 +151,17 @@ static void kvm_pmu_release_perf_event(struct kvm_pmc *pmc)
*/
static void kvm_pmu_stop_counter(struct kvm_vcpu *vcpu, struct kvm_pmc *pmc)
{
- u64 counter, reg, val;
+ u64 reg, val;
if (!pmc->perf_event)
return;
- counter = kvm_pmu_get_counter_value(vcpu, pmc->idx);
+ val = kvm_pmu_get_counter_value(vcpu, pmc->idx);
- if (pmc->idx == ARMV8_PMU_CYCLE_IDX) {
+ if (pmc->idx == ARMV8_PMU_CYCLE_IDX)
reg = PMCCNTR_EL0;
- val = counter;
- } else {
+ else
reg = PMEVCNTR0_EL0 + pmc->idx;
- val = lower_32_bits(counter);
- }
__vcpu_sys_reg(vcpu, reg) = val;
@@ -416,7 +413,8 @@ static void kvm_pmu_counter_increment(struct kvm_vcpu *vcpu,
/* Increment this counter */
reg = __vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) + 1;
- reg = lower_32_bits(reg);
+ if (!kvm_pmu_idx_is_64bit(vcpu, i))
+ reg = lower_32_bits(reg);
__vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) = reg;
/* No overflow? move on */
--
2.34.1
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next prev parent reply other threads:[~2022-11-07 8:56 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-07 8:54 [PATCH v3 00/14] KVM: arm64: PMU: Fixing chained events, and PMUv3p5 support Marc Zyngier
2022-11-07 8:54 ` [PATCH v3 01/14] arm64: Add ID_DFR0_EL1.PerfMon values for PMUv3p7 and IMP_DEF Marc Zyngier
2022-11-07 8:54 ` [PATCH v3 02/14] KVM: arm64: PMU: Align chained counter implementation with architecture pseudocode Marc Zyngier
2022-11-12 7:55 ` Reiji Watanabe
2022-11-12 12:39 ` Marc Zyngier
2022-11-12 17:11 ` Reiji Watanabe
2022-11-07 8:54 ` [PATCH v3 03/14] KVM: arm64: PMU: Always advertise the CHAIN event Marc Zyngier
2022-11-07 8:54 ` [PATCH v3 04/14] KVM: arm64: PMU: Distinguish between 64bit counter and 64bit overflow Marc Zyngier
2022-11-07 8:54 ` [PATCH v3 05/14] KVM: arm64: PMU: Narrow the overflow checking when required Marc Zyngier
2022-11-07 8:54 ` Marc Zyngier [this message]
2022-11-07 8:54 ` [PATCH v3 07/14] KVM: arm64: PMU: Add counter_index_to_*reg() helpers Marc Zyngier
2022-11-07 8:54 ` [PATCH v3 08/14] KVM: arm64: PMU: Simplify setting a counter to a specific value Marc Zyngier
2022-11-07 8:54 ` [PATCH v3 09/14] KVM: arm64: PMU: Do not let AArch32 change the counters' top 32 bits Marc Zyngier
2022-11-07 8:54 ` [PATCH v3 10/14] KVM: arm64: PMU: Move the ID_AA64DFR0_EL1.PMUver limit to VM creation Marc Zyngier
2022-11-07 8:54 ` [PATCH v3 11/14] KVM: arm64: PMU: Allow ID_AA64DFR0_EL1.PMUver to be set from userspace Marc Zyngier
2022-11-08 5:38 ` Reiji Watanabe
2022-11-13 10:21 ` Marc Zyngier
2022-11-07 8:54 ` [PATCH v3 12/14] KVM: arm64: PMU: Allow ID_DFR0_EL1.PerfMon " Marc Zyngier
2022-11-07 8:54 ` [PATCH v3 13/14] KVM: arm64: PMU: Implement PMUv3p5 long counter support Marc Zyngier
2022-11-07 8:54 ` [PATCH v3 14/14] KVM: arm64: PMU: Allow PMUv3p5 to be exposed to the guest Marc Zyngier
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