From: Marc Zyngier <maz@kernel.org>
To: linux-arm-kernel@lists.infradead.org,
<kvmarm@lists.cs.columbia.edu>, <kvmarm@lists.linux.dev>,
kvm@vger.kernel.org
Cc: James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
Ricardo Koller <ricarkol@google.com>,
Reiji Watanabe <reijiw@google.com>
Subject: [PATCH v3 08/14] KVM: arm64: PMU: Simplify setting a counter to a specific value
Date: Mon, 7 Nov 2022 08:54:29 +0000 [thread overview]
Message-ID: <20221107085435.2581641-9-maz@kernel.org> (raw)
In-Reply-To: <20221107085435.2581641-1-maz@kernel.org>
kvm_pmu_set_counter_value() is pretty odd, as it tries to update
the counter value while taking into account the value that is
currently held by the running perf counter.
This is not only complicated, this is quite wrong. Nowhere in
the architecture is it said that the counter would be offset
by something that is pending. The counter should be updated
with the value set by SW, and start counting from there if
required.
Remove the odd computation and just assign the provided value
after having released the perf event (which is then restarted).
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/kvm/pmu-emul.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
index 44ad0fdba4db..03b761a63f5f 100644
--- a/arch/arm64/kvm/pmu-emul.c
+++ b/arch/arm64/kvm/pmu-emul.c
@@ -23,6 +23,7 @@ static LIST_HEAD(arm_pmus);
static DEFINE_MUTEX(arm_pmus_lock);
static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx);
+static void kvm_pmu_release_perf_event(struct kvm_pmc *pmc);
static u32 kvm_pmu_event_mask(struct kvm *kvm)
{
@@ -131,8 +132,10 @@ void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val)
if (!kvm_vcpu_has_pmu(vcpu))
return;
+ kvm_pmu_release_perf_event(&vcpu->arch.pmu.pmc[select_idx]);
+
reg = counter_index_to_reg(select_idx);
- __vcpu_sys_reg(vcpu, reg) += (s64)val - kvm_pmu_get_counter_value(vcpu, select_idx);
+ __vcpu_sys_reg(vcpu, reg) = val;
/* Recreate the perf event to reflect the updated sample_period */
kvm_pmu_create_perf_event(vcpu, select_idx);
--
2.34.1
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next prev parent reply other threads:[~2022-11-07 8:57 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-07 8:54 [PATCH v3 00/14] KVM: arm64: PMU: Fixing chained events, and PMUv3p5 support Marc Zyngier
2022-11-07 8:54 ` [PATCH v3 01/14] arm64: Add ID_DFR0_EL1.PerfMon values for PMUv3p7 and IMP_DEF Marc Zyngier
2022-11-07 8:54 ` [PATCH v3 02/14] KVM: arm64: PMU: Align chained counter implementation with architecture pseudocode Marc Zyngier
2022-11-12 7:55 ` Reiji Watanabe
2022-11-12 12:39 ` Marc Zyngier
2022-11-12 17:11 ` Reiji Watanabe
2022-11-07 8:54 ` [PATCH v3 03/14] KVM: arm64: PMU: Always advertise the CHAIN event Marc Zyngier
2022-11-07 8:54 ` [PATCH v3 04/14] KVM: arm64: PMU: Distinguish between 64bit counter and 64bit overflow Marc Zyngier
2022-11-07 8:54 ` [PATCH v3 05/14] KVM: arm64: PMU: Narrow the overflow checking when required Marc Zyngier
2022-11-07 8:54 ` [PATCH v3 06/14] KVM: arm64: PMU: Only narrow counters that are not 64bit wide Marc Zyngier
2022-11-07 8:54 ` [PATCH v3 07/14] KVM: arm64: PMU: Add counter_index_to_*reg() helpers Marc Zyngier
2022-11-07 8:54 ` Marc Zyngier [this message]
2022-11-07 8:54 ` [PATCH v3 09/14] KVM: arm64: PMU: Do not let AArch32 change the counters' top 32 bits Marc Zyngier
2022-11-07 8:54 ` [PATCH v3 10/14] KVM: arm64: PMU: Move the ID_AA64DFR0_EL1.PMUver limit to VM creation Marc Zyngier
2022-11-07 8:54 ` [PATCH v3 11/14] KVM: arm64: PMU: Allow ID_AA64DFR0_EL1.PMUver to be set from userspace Marc Zyngier
2022-11-08 5:38 ` Reiji Watanabe
2022-11-13 10:21 ` Marc Zyngier
2022-11-07 8:54 ` [PATCH v3 12/14] KVM: arm64: PMU: Allow ID_DFR0_EL1.PerfMon " Marc Zyngier
2022-11-07 8:54 ` [PATCH v3 13/14] KVM: arm64: PMU: Implement PMUv3p5 long counter support Marc Zyngier
2022-11-07 8:54 ` [PATCH v3 14/14] KVM: arm64: PMU: Allow PMUv3p5 to be exposed to the guest Marc Zyngier
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