* [PATCH V3 01/14] arm64: dts: imx8mp: add mlmix power domain
2022-11-08 2:18 [PATCH V3 00/14] arm64: dts: imx8m-evk: misc dts update Peng Fan (OSS)
@ 2022-11-08 2:18 ` Peng Fan (OSS)
2022-11-08 2:18 ` [PATCH V3 02/14] arm64: dts: imx8mp-evk: correct pcie pad settings Peng Fan (OSS)
` (12 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Peng Fan (OSS) @ 2022-11-08 2:18 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, devicetree, linux-kernel,
linux-arm-kernel, Peng Fan, Marco Felsch
From: Peng Fan <peng.fan@nxp.com>
Add mlmix power domain
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Marco Felsch <m.felsch@pengutronix.de>
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 7be02cd100cf..08704d2d9fdf 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -631,6 +631,14 @@ pgc_vpu_vc8000e: power-domain@22 {
reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
};
+
+ pgc_mlmix: power-domain@24 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MP_POWER_DOMAIN_MLMIX>;
+ clocks = <&clk IMX8MP_CLK_ML_AXI>,
+ <&clk IMX8MP_CLK_ML_AHB>,
+ <&clk IMX8MP_CLK_NPU_ROOT>;
+ };
};
};
};
--
2.37.1
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH V3 02/14] arm64: dts: imx8mp-evk: correct pcie pad settings
2022-11-08 2:18 [PATCH V3 00/14] arm64: dts: imx8m-evk: misc dts update Peng Fan (OSS)
2022-11-08 2:18 ` [PATCH V3 01/14] arm64: dts: imx8mp: add mlmix power domain Peng Fan (OSS)
@ 2022-11-08 2:18 ` Peng Fan (OSS)
2022-11-08 2:18 ` [PATCH V3 03/14] ARM64: dts: imx8mp-evk: add pwm support Peng Fan (OSS)
` (11 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Peng Fan (OSS) @ 2022-11-08 2:18 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, devicetree, linux-kernel,
linux-arm-kernel, Peng Fan, Marco Felsch
From: Peng Fan <peng.fan@nxp.com>
According to RM bit layout, BIT3 and BIT0 are reserved.
8 7 6 5 4 3 2 1 0
PE HYS PUE ODE FSEL X DSE X
Although function is not broken, we should not set reserved bit.
Fixes: d50650500064 ("arm64: dts: imx8mp-evk: Add PCIe support")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
---
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 9f1469db554d..b4c1ef2559f2 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -544,14 +544,14 @@ MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2
pinctrl_pcie0: pcie0grp {
fsl,pins = <
- MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 /* open drain, pull up */
- MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41
+ MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60 /* open drain, pull up */
+ MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x40
>;
};
pinctrl_pcie0_reg: pcie0reggrp {
fsl,pins = <
- MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41
+ MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40
>;
};
--
2.37.1
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH V3 03/14] ARM64: dts: imx8mp-evk: add pwm support
2022-11-08 2:18 [PATCH V3 00/14] arm64: dts: imx8m-evk: misc dts update Peng Fan (OSS)
2022-11-08 2:18 ` [PATCH V3 01/14] arm64: dts: imx8mp: add mlmix power domain Peng Fan (OSS)
2022-11-08 2:18 ` [PATCH V3 02/14] arm64: dts: imx8mp-evk: correct pcie pad settings Peng Fan (OSS)
@ 2022-11-08 2:18 ` Peng Fan (OSS)
2022-11-08 2:18 ` [PATCH V3 04/14] arm64: dts: imx8mp-evk: enable uart1/3 ports Peng Fan (OSS)
` (10 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Peng Fan (OSS) @ 2022-11-08 2:18 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, devicetree, linux-kernel,
linux-arm-kernel, Clark Wang, Fugang Duan, Peng Fan, Marco Felsch
From: Clark Wang <xiaoning.wang@nxp.com>
Enable pwm1/2/4 support.
Enable pwm1 on pin GPIO1_IO01 for DSI_BL_PWM
pwm2 on pin GPIO1_IO11 for LVDS_BL_PWM
pwm4 on pin SAI5_RXFS for J21-32
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
---
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 36 ++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index b4c1ef2559f2..e323e6f4b7e5 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -390,6 +390,24 @@ &pcie {
status = "okay";
};
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
+
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+ status = "okay";
+};
+
&snvs_pwrkey {
status = "okay";
};
@@ -567,6 +585,24 @@ MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* Input pull-up. */
>;
};
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116
+ >;
+ };
+
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116
+ >;
+ };
+
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
--
2.37.1
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH V3 04/14] arm64: dts: imx8mp-evk: enable uart1/3 ports
2022-11-08 2:18 [PATCH V3 00/14] arm64: dts: imx8m-evk: misc dts update Peng Fan (OSS)
` (2 preceding siblings ...)
2022-11-08 2:18 ` [PATCH V3 03/14] ARM64: dts: imx8mp-evk: add pwm support Peng Fan (OSS)
@ 2022-11-08 2:18 ` Peng Fan (OSS)
2022-11-08 2:18 ` [PATCH V3 05/14] arm64: dts: imx8mp-evk: enable fspi nor on imx8mp evk Peng Fan (OSS)
` (9 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Peng Fan (OSS) @ 2022-11-08 2:18 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, devicetree, linux-kernel,
linux-arm-kernel, Peng Fan, Marco Felsch
From: Peng Fan <peng.fan@nxp.com>
Enable uart1/3 ports for evk board.
Configure the clock to source from IMX8MP_SYS_PLL1_80M, because the uart
could only support max 1.5M buadrate if using OSC_24M as clock source.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
---
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 36 ++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index e323e6f4b7e5..29472502d547 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -412,6 +412,15 @@ &snvs_pwrkey {
status = "okay";
};
+&uart1 { /* BT */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ assigned-clocks = <&clk IMX8MP_CLK_UART1>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
&uart2 {
/* console */
pinctrl-names = "default";
@@ -434,6 +443,15 @@ &usb_dwc3_1 {
status = "okay";
};
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ assigned-clocks = <&clk IMX8MP_CLK_UART3>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
&usdhc2 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
assigned-clock-rates = <400000000>;
@@ -609,6 +627,15 @@ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
>;
};
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
+ MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
+ MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
+ MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
+ >;
+ };
+
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
@@ -622,6 +649,15 @@ MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10
>;
};
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
+ MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
+ MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140
+ MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
+ >;
+ };
+
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
--
2.37.1
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH V3 05/14] arm64: dts: imx8mp-evk: enable fspi nor on imx8mp evk
2022-11-08 2:18 [PATCH V3 00/14] arm64: dts: imx8m-evk: misc dts update Peng Fan (OSS)
` (3 preceding siblings ...)
2022-11-08 2:18 ` [PATCH V3 04/14] arm64: dts: imx8mp-evk: enable uart1/3 ports Peng Fan (OSS)
@ 2022-11-08 2:18 ` Peng Fan (OSS)
2022-11-08 2:18 ` [PATCH V3 06/14] arm64: dts: imx8mp-evk: enable I2C2 node Peng Fan (OSS)
` (8 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Peng Fan (OSS) @ 2022-11-08 2:18 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, devicetree, linux-kernel,
linux-arm-kernel, Han Xu, Frank Li, Peng Fan, Marco Felsch
From: Han Xu <han.xu@nxp.com>
enable fspi nor on imx8mp evk dts
Reviewed-by: Frank Li <frank.li@nxp.com>
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
---
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 25 ++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 29472502d547..4164f69a89a6 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -85,6 +85,20 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
};
};
+&flexspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi0>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <80000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ };
+};
+
&A53_0 {
cpu-supply = <®_arm>;
};
@@ -551,6 +565,17 @@ MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */
>;
};
+ pinctrl_flexspi0: flexspi0grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
+ MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
+ MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
+ MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
+ MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
+ MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
+ >;
+ };
+
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140
--
2.37.1
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH V3 06/14] arm64: dts: imx8mp-evk: enable I2C2 node
2022-11-08 2:18 [PATCH V3 00/14] arm64: dts: imx8m-evk: misc dts update Peng Fan (OSS)
` (4 preceding siblings ...)
2022-11-08 2:18 ` [PATCH V3 05/14] arm64: dts: imx8mp-evk: enable fspi nor on imx8mp evk Peng Fan (OSS)
@ 2022-11-08 2:18 ` Peng Fan (OSS)
2022-11-08 2:18 ` [PATCH V3 07/14] arm64: dts: imx8mn-evk: update vdd_soc dvs voltage Peng Fan (OSS)
` (7 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Peng Fan (OSS) @ 2022-11-08 2:18 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, devicetree, linux-kernel,
linux-arm-kernel, Peng Fan, Marco Felsch
From: Peng Fan <peng.fan@nxp.com>
Enable I2C node for i.MX8MP-EVK
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
---
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 4164f69a89a6..878d4a752090 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -331,6 +331,13 @@ LDO5 {
};
};
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
@@ -589,6 +596,13 @@ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
>;
};
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
+ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
+ >;
+ };
+
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
--
2.37.1
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH V3 07/14] arm64: dts: imx8mn-evk: update vdd_soc dvs voltage
2022-11-08 2:18 [PATCH V3 00/14] arm64: dts: imx8m-evk: misc dts update Peng Fan (OSS)
` (5 preceding siblings ...)
2022-11-08 2:18 ` [PATCH V3 06/14] arm64: dts: imx8mp-evk: enable I2C2 node Peng Fan (OSS)
@ 2022-11-08 2:18 ` Peng Fan (OSS)
2022-11-08 2:18 ` [PATCH V3 08/14] arm64: dts: imx8mn-evk: set off-on-delay-us in regulator Peng Fan (OSS)
` (6 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Peng Fan (OSS) @ 2022-11-08 2:18 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, devicetree, linux-kernel,
linux-arm-kernel, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Per schematic, BUCK1 is for VDD_SOC&DRAM&PU_0V9. The nxp,dvs-run-voltage
and nxp,dvs-standby-voltage need set for BUCK1, not BUCK2.
BUCK2 is for A53, which is handled by DVFS, so no need dvs property.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mn-evk.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
index 4eb467df5ba7..a5a7d74ec1d5 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
@@ -47,6 +47,8 @@ buck1: BUCK1{
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
+ nxp,dvs-run-voltage = <950000>;
+ nxp,dvs-standby-voltage = <750000>;
};
buck2: BUCK2 {
@@ -56,8 +58,6 @@ buck2: BUCK2 {
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
- nxp,dvs-run-voltage = <950000>;
- nxp,dvs-standby-voltage = <850000>;
};
buck4: BUCK4{
--
2.37.1
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH V3 08/14] arm64: dts: imx8mn-evk: set off-on-delay-us in regulator
2022-11-08 2:18 [PATCH V3 00/14] arm64: dts: imx8m-evk: misc dts update Peng Fan (OSS)
` (6 preceding siblings ...)
2022-11-08 2:18 ` [PATCH V3 07/14] arm64: dts: imx8mn-evk: update vdd_soc dvs voltage Peng Fan (OSS)
@ 2022-11-08 2:18 ` Peng Fan (OSS)
2022-11-08 2:18 ` [PATCH V3 09/14] arm64: dts: imx8mn-evk: add i2c gpio recovery settings Peng Fan (OSS)
` (5 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Peng Fan (OSS) @ 2022-11-08 2:18 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, devicetree, linux-kernel,
linux-arm-kernel, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Some SD Card controller and power circuitry has increased capacitance,
so the usual toggling of regulator to power the card off and on
is insufficient.
According to SD spec, for sd card power reset operation, the sd card
supply voltage needs to be lower than 0.5v and keep over 1ms, otherwise,
next time power back the sd card supply voltage to 3.3v, sd card can't
support SD3.0 mode again.
This patch add the off-on-delay-us, make sure the sd power reset behavior
is align with the specification. Without this patch, when do quick system
suspend/resume test, some sd card can't work at SD3.0 mode after system
resume back.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
index 261c36540079..2b4395854283 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
@@ -36,6 +36,7 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ off-on-delay-us = <12000>;
enable-active-high;
};
--
2.37.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH V3 09/14] arm64: dts: imx8mn-evk: add i2c gpio recovery settings
2022-11-08 2:18 [PATCH V3 00/14] arm64: dts: imx8m-evk: misc dts update Peng Fan (OSS)
` (7 preceding siblings ...)
2022-11-08 2:18 ` [PATCH V3 08/14] arm64: dts: imx8mn-evk: set off-on-delay-us in regulator Peng Fan (OSS)
@ 2022-11-08 2:18 ` Peng Fan (OSS)
2022-11-08 2:18 ` [PATCH V3 10/14] arm64: dts: imx8mn-evk: enable uart1 Peng Fan (OSS)
` (4 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Peng Fan (OSS) @ 2022-11-08 2:18 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, devicetree, linux-kernel,
linux-arm-kernel, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Add I2C gpio recovery iomuxc settings
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 24 +++++++++++++++++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
index 2b4395854283..1971f095e4c2 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
@@ -160,8 +160,11 @@ &i2c1 {
&i2c2 {
clock-frequency = <400000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
status = "okay";
ptn5110: tcpc@50 {
@@ -196,8 +199,11 @@ typec1_con: connector {
&i2c3 {
clock-frequency = <400000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
status = "okay";
pca6416: gpio@20 {
@@ -370,6 +376,13 @@ MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
+ pinctrl_i2c2_gpio: i2c2grp-gpio {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3
+ MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3
+ >;
+ };
+
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
@@ -377,6 +390,13 @@ MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
+ pinctrl_i2c3_gpio: i2c3grp-gpio {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3
+ MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3
+ >;
+ };
+
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
--
2.37.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH V3 10/14] arm64: dts: imx8mn-evk: enable uart1
2022-11-08 2:18 [PATCH V3 00/14] arm64: dts: imx8m-evk: misc dts update Peng Fan (OSS)
` (8 preceding siblings ...)
2022-11-08 2:18 ` [PATCH V3 09/14] arm64: dts: imx8mn-evk: add i2c gpio recovery settings Peng Fan (OSS)
@ 2022-11-08 2:18 ` Peng Fan (OSS)
2022-11-08 2:18 ` [PATCH V3 11/14] arm64: dts: imx8mn-evk: enable usdhc1 Peng Fan (OSS)
` (3 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Peng Fan (OSS) @ 2022-11-08 2:18 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, devicetree, linux-kernel,
linux-arm-kernel, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Enable uart1 for BT usage
Configure the clock to source from IMX8MN_SYS_PLL1_80M, because the uart
could only support max 1.5M buadrate if using OSC_24M as clock source.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
index 1971f095e4c2..12dc5d398a03 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
@@ -247,6 +247,15 @@ &spdif1 {
status = "okay";
};
+&uart1 { /* BT */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ assigned-clocks = <&clk IMX8MN_CLK_UART1>;
+ assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
&uart2 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
@@ -440,6 +449,15 @@ MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
>;
};
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
+ MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
+ MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
+ MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
+ >;
+ };
+
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
--
2.37.1
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH V3 11/14] arm64: dts: imx8mn-evk: enable usdhc1
2022-11-08 2:18 [PATCH V3 00/14] arm64: dts: imx8m-evk: misc dts update Peng Fan (OSS)
` (9 preceding siblings ...)
2022-11-08 2:18 ` [PATCH V3 10/14] arm64: dts: imx8mn-evk: enable uart1 Peng Fan (OSS)
@ 2022-11-08 2:18 ` Peng Fan (OSS)
2022-11-08 2:18 ` [PATCH V3 12/14] arm64: dts: imx8mm-evk: Enable usdhc1 to support wifi Peng Fan (OSS)
` (2 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Peng Fan (OSS) @ 2022-11-08 2:18 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, devicetree, linux-kernel,
linux-arm-kernel, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Enable usdhc1 for wlan usage, the wifi device node not included.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 67 +++++++++++++++++++
1 file changed, 67 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
index 12dc5d398a03..8d498718e0ca 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
@@ -28,6 +28,13 @@ memory@40000000 {
reg = <0x0 0x40000000 0 0x80000000>;
};
+ usdhc1_pwrseq: usdhc1_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1_gpio>;
+ reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+ };
+
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
@@ -271,6 +278,20 @@ &uart3 {
status = "okay";
};
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>;
+ bus-width = <4>;
+ keep-power-in-suspend;
+ non-removable;
+ wakeup-source;
+ fsl,sdio-async-interrupt-enabled;
+ mmc-pwrseq = <&usdhc1_pwrseq>;
+ status = "okay";
+};
+
&usbotg1 {
dr_mode = "otg";
hnp-disable;
@@ -474,6 +495,45 @@ MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140
>;
};
+ pinctrl_usdhc1_gpio: usdhc1grpgpio {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+ MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+ MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+ MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+ MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+ MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
+ MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
+ MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
+ MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
+ MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
+ MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
+ MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
+ MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
+ MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
+ MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
+ MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
+ >;
+ };
+
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
@@ -569,4 +629,11 @@ pinctrl_wdog: wdoggrp {
MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
>;
};
+
+ pinctrl_wlan: wlangrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141
+ MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x159
+ >;
+ };
};
--
2.37.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH V3 12/14] arm64: dts: imx8mm-evk: Enable usdhc1 to support wifi
2022-11-08 2:18 [PATCH V3 00/14] arm64: dts: imx8m-evk: misc dts update Peng Fan (OSS)
` (10 preceding siblings ...)
2022-11-08 2:18 ` [PATCH V3 11/14] arm64: dts: imx8mn-evk: enable usdhc1 Peng Fan (OSS)
@ 2022-11-08 2:18 ` Peng Fan (OSS)
2022-11-08 9:06 ` Marco Felsch
2022-11-08 2:18 ` [PATCH V3 13/14] arm64: dts: imx8m[m,q]-evk: change to use off-on-delay-us in regulator Peng Fan (OSS)
2022-11-08 2:18 ` [PATCH V3 14/14] arm64: dts: imx8mm-evk: add vcc supply for pca6416 Peng Fan (OSS)
13 siblings, 1 reply; 16+ messages in thread
From: Peng Fan (OSS) @ 2022-11-08 2:18 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, devicetree, linux-kernel,
linux-arm-kernel, Sherry Sun, Peng Fan
From: Sherry Sun <sherry.sun@nxp.com>
Enable usdhc1 which is used for wifi.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 23 +++++++++++
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 39 +++++++++++++++++++
2 files changed, 62 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
index a2b24d4d4e3e..898735965ac9 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
@@ -15,6 +15,17 @@ / {
aliases {
spi0 = &flexspi;
};
+
+ reg_sd1_vmmc: sd1_regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "WLAN_EN";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>;
+ off-on-delay-us = <20000>;
+ startup-delay-us = <100>;
+ enable-active-high;
+ };
};
&ddrc {
@@ -53,6 +64,18 @@ flash@0 {
};
};
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
+ bus-width = <4>;
+ vmmc-supply = <®_sd1_vmmc>;
+ keep-power-in-suspend;
+ non-removable;
+ status = "okay";
+};
+
&usdhc3 {
assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
assigned-clock-rates = <400000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
index 7d6317d95b13..ce450965e837 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
@@ -559,6 +559,45 @@ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
+ pinctrl_usdhc1_gpio: usdhc1grpgpio {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
+ >;
+ };
+
pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
--
2.37.1
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^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH V3 12/14] arm64: dts: imx8mm-evk: Enable usdhc1 to support wifi
2022-11-08 2:18 ` [PATCH V3 12/14] arm64: dts: imx8mm-evk: Enable usdhc1 to support wifi Peng Fan (OSS)
@ 2022-11-08 9:06 ` Marco Felsch
0 siblings, 0 replies; 16+ messages in thread
From: Marco Felsch @ 2022-11-08 9:06 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer, Sherry Sun,
devicetree, Peng Fan, linux-kernel, linux-imx, kernel, festevam,
linux-arm-kernel
On 22-11-08, Peng Fan (OSS) wrote:
> From: Sherry Sun <sherry.sun@nxp.com>
>
> Enable usdhc1 which is used for wifi.
>
> Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 23 +++++++++++
> arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 39 +++++++++++++++++++
> 2 files changed, 62 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> index a2b24d4d4e3e..898735965ac9 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> @@ -15,6 +15,17 @@ / {
> aliases {
> spi0 = &flexspi;
> };
> +
> + reg_sd1_vmmc: sd1_regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "WLAN_EN";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>;
> + off-on-delay-us = <20000>;
> + startup-delay-us = <100>;
> + enable-active-high;
> + };
This is a bit inconsistent with the imx8mn-evk.dtsi where you used
mmc-pwrseq instead of vmmc-supply. Also Do you really need the delay
here?
Regards,
Marco
> };
>
> &ddrc {
> @@ -53,6 +64,18 @@ flash@0 {
> };
> };
>
> +&usdhc1 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
> + bus-width = <4>;
> + vmmc-supply = <®_sd1_vmmc>;
> + keep-power-in-suspend;
> + non-removable;
> + status = "okay";
> +};
> +
> &usdhc3 {
> assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
> assigned-clock-rates = <400000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> index 7d6317d95b13..ce450965e837 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> @@ -559,6 +559,45 @@ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
> >;
> };
>
> + pinctrl_usdhc1_gpio: usdhc1grpgpio {
> + fsl,pins = <
> + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
> + >;
> + };
> +
> + pinctrl_usdhc1: usdhc1grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
> + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
> + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
> + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
> + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
> + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
> + >;
> + };
> +
> + pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
> + fsl,pins = <
> + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
> + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
> + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
> + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
> + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
> + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
> + >;
> + };
> +
> + pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
> + fsl,pins = <
> + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
> + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
> + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
> + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
> + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
> + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
> + >;
> + };
> +
> pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
> fsl,pins = <
> MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
> --
> 2.37.1
>
>
>
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^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH V3 13/14] arm64: dts: imx8m[m,q]-evk: change to use off-on-delay-us in regulator
2022-11-08 2:18 [PATCH V3 00/14] arm64: dts: imx8m-evk: misc dts update Peng Fan (OSS)
` (11 preceding siblings ...)
2022-11-08 2:18 ` [PATCH V3 12/14] arm64: dts: imx8mm-evk: Enable usdhc1 to support wifi Peng Fan (OSS)
@ 2022-11-08 2:18 ` Peng Fan (OSS)
2022-11-08 2:18 ` [PATCH V3 14/14] arm64: dts: imx8mm-evk: add vcc supply for pca6416 Peng Fan (OSS)
13 siblings, 0 replies; 16+ messages in thread
From: Peng Fan (OSS) @ 2022-11-08 2:18 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, devicetree, linux-kernel,
linux-arm-kernel, Haibo Chen, Peng Fan
From: Haibo Chen <haibo.chen@nxp.com>
Some SD Card controller and power circuitry has increased capacitance,
so the usual toggling of regulator to power the card off and on
is insufficient.
According to SD spec, for sd card power reset operation, the sd card
supply voltage needs to be lower than 0.5v and keep over 1ms, otherwise,
next time power back the sd card supply voltage to 3.3v, sd card can't
support SD3.0 mode again.
This patch add the off-on-delay-us, make sure the sd power reset behavior
is align with the specification. Without this patch, when do quick system
suspend/resume test, some sd card can't work at SD3.0 mode after system
resume back.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
index ce450965e837..fdbcd2483efc 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
@@ -56,6 +56,7 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ off-on-delay-us = <20000>;
enable-active-high;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index 82387b9cb800..07d9fb2aacf8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -46,6 +46,7 @@ reg_usdhc2_vmmc: regulator-vsd-3v3 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ off-on-delay-us = <20000>;
enable-active-high;
};
--
2.37.1
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH V3 14/14] arm64: dts: imx8mm-evk: add vcc supply for pca6416
2022-11-08 2:18 [PATCH V3 00/14] arm64: dts: imx8m-evk: misc dts update Peng Fan (OSS)
` (12 preceding siblings ...)
2022-11-08 2:18 ` [PATCH V3 13/14] arm64: dts: imx8m[m,q]-evk: change to use off-on-delay-us in regulator Peng Fan (OSS)
@ 2022-11-08 2:18 ` Peng Fan (OSS)
13 siblings, 0 replies; 16+ messages in thread
From: Peng Fan (OSS) @ 2022-11-08 2:18 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, devicetree, linux-kernel,
linux-arm-kernel, Adrian Alonso, Shengjiu Wang, Peng Fan
From: Adrian Alonso <adrian.alonso@nxp.com>
pca6146 requires vcc-supply to work on i.MX8MM-EVK board.
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
index fdbcd2483efc..31144aefe0ba 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
@@ -344,6 +344,7 @@ pca6416: gpio@20 {
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
+ vcc-supply = <&buck4_reg>;
};
};
--
2.37.1
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^ permalink raw reply related [flat|nested] 16+ messages in thread