From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DF83CC4332F for ; Fri, 11 Nov 2022 02:57:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=YSPwi4UZdBAOjzUJkyaBB7ee1jlKkajEPK1KQMGuknE=; b=PMo+Dms2fMgjqM gakoCCIAeIxbSozRXNBYzaMXYPBy5iGKz7zL6VH4BvTDZPtj3pVCPgDs9PrWMs13/iscIdP0ESTcb pPRR2EUtyKl9HidpqTEMCzAiSWxhObKtfLP2fDokT01Z0vZhMF6IWVFoUgRmjzjQi7ragzzN6yjBP epgyJ7AuQSEAGn5ms1/ws2n9TLwu0d+rRBZBOIxJYbeEcZ3MBQJb2a1UpBpX0J3vwdballOCkdI7f rV0D5bw/AEpPPIRumOVAnnRhURkt0gUPU/eQF4Dq4rC1KxhdZxQ7VTvADIRngMo/dfIgPi9iMx2l1 ClzAAZ5iR6oCRUS8w8ww==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1otKD8-00CLkk-4f; Fri, 11 Nov 2022 02:56:06 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1otKD5-00CLiW-7y for linux-arm-kernel@lists.infradead.org; Fri, 11 Nov 2022 02:56:05 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 4799F61134; Fri, 11 Nov 2022 02:56:02 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 94EF5C433D6; Fri, 11 Nov 2022 02:55:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1668135361; bh=PnVF2jbu5Vi4C6B/3+qaYjq7wicZtUJxbK4ohcpyQys=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=NPjoPPdY1bhnj1FMtZt5Bmzjvx3ViTblibo485m0wngFE/SZu+W+yrmCKvzqKeFYv 1VWH6gcqygqKNcgMOk99XmTNn9uy9Iflfj5mY58zdNetQjIbUBD8G9K0716rXnRNSg 2uxLlVt/clQqf/vp+jyHrfiRZwXD73Aex6af54TRe4xv8H6/CneKPR0+sUyktc9P3l zJY3XH36Ieg1hHs182gEifcP+lR8o+ndxBdV12gqLVDJYcVwEw7VGFQHDO2EMm9O0q 9j/sEUJu2lXOF1BW8W47sM+rVQJQ31jtzj1s27J1c2iO59WexR40VVnempwV2lfu1Z d8UJ5om7E1uzA== Date: Fri, 11 Nov 2022 10:55:53 +0800 From: Shawn Guo To: Pierre Gondois Cc: linux-kernel@vger.kernel.org, Rob.Herring@arm.com, Li Yang , Rob Herring , Krzysztof Kozlowski , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Chester Lin , Andreas =?iso-8859-1?Q?F=E4rber?= , Matthias Brugger , NXP S32 Linux Team , Peng Fan , Jacky Bai , Sudeep Holla , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: Re: [PATCH 07/20] arm64: dts: Update cache properties for freescale Message-ID: <20221111025553.GJ125525@dragon> References: <20221031091956.531935-1-pierre.gondois@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221031091956.531935-1-pierre.gondois@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221110_185603_396598_CC4E803B X-CRM114-Status: GOOD ( 17.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Oct 31, 2022 at 10:19:51AM +0100, Pierre Gondois wrote: > The DeviceTree Specification v0.3 specifies that the cache node > 'compatible' and 'cache-level' properties are 'required'. Cf. > s3.8 Multi-level and Shared Cache Nodes > > The recently added init_of_cache_level() function checks > these properties. Add them if missing. > > Signed-off-by: Pierre Gondois Looks good to me. Should I pick it up on IMX tree, or it needs to go as part of the series (via other tree)? Shawn > --- > arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 1 + > arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 + > arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 + > arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 4 ++++ > arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 4 ++++ > arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 1 + > arch/arm64/boot/dts/freescale/s32g2.dtsi | 2 ++ > arch/arm64/boot/dts/freescale/s32v234.dtsi | 2 ++ > 8 files changed, 16 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi > index 5627dd7734f3..ed0cc1a5d17e 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi > @@ -46,6 +46,7 @@ cpu1: cpu@1 { > > l2: l2-cache { > compatible = "cache"; > + cache-level = <2>; > }; > }; > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi > index ca3d5a90d6d4..c8b1202d2584 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi > @@ -83,6 +83,7 @@ cpu3: cpu@3 { > > l2: l2-cache { > compatible = "cache"; > + cache-level = <2>; > }; > }; > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi > index feab604322cf..4590bdc076b7 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi > @@ -78,6 +78,7 @@ cpu3: cpu@3 { > > l2: l2-cache { > compatible = "cache"; > + cache-level = <2>; > }; > }; > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi > index 6f6667b70028..2a7e13b6ef8a 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi > +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi > @@ -95,18 +95,22 @@ cpu7: cpu@301 { > > cluster0_l2: l2-cache0 { > compatible = "cache"; > + cache-level = <2>; > }; > > cluster1_l2: l2-cache1 { > compatible = "cache"; > + cache-level = <2>; > }; > > cluster2_l2: l2-cache2 { > compatible = "cache"; > + cache-level = <2>; > }; > > cluster3_l2: l2-cache3 { > compatible = "cache"; > + cache-level = <2>; > }; > > CPU_PW20: cpu-pw20 { > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi > index c3dc38188c17..c12c86915ec8 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi > +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi > @@ -95,18 +95,22 @@ cpu7: cpu@301 { > > cluster0_l2: l2-cache0 { > compatible = "cache"; > + cache-level = <2>; > }; > > cluster1_l2: l2-cache1 { > compatible = "cache"; > + cache-level = <2>; > }; > > cluster2_l2: l2-cache2 { > compatible = "cache"; > + cache-level = <2>; > }; > > cluster3_l2: l2-cache3 { > compatible = "cache"; > + cache-level = <2>; > }; > > CPU_PW20: cpu-pw20 { > diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > index 60c1b018bf03..187353458673 100644 > --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > @@ -50,6 +50,7 @@ A35_1: cpu@1 { > > A35_L2: l2-cache0 { > compatible = "cache"; > + cache-level = <2>; > }; > }; > > diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi > index 824d401e7a2c..d8c82da88ca0 100644 > --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi > +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi > @@ -52,10 +52,12 @@ cpu3: cpu@101 { > > cluster0_l2: l2-cache0 { > compatible = "cache"; > + cache-level = <2>; > }; > > cluster1_l2: l2-cache1 { > compatible = "cache"; > + cache-level = <2>; > }; > }; > > diff --git a/arch/arm64/boot/dts/freescale/s32v234.dtsi b/arch/arm64/boot/dts/freescale/s32v234.dtsi > index ba0b5305d481..3e306218d533 100644 > --- a/arch/arm64/boot/dts/freescale/s32v234.dtsi > +++ b/arch/arm64/boot/dts/freescale/s32v234.dtsi > @@ -61,10 +61,12 @@ cpu3: cpu@101 { > > cluster0_l2_cache: l2-cache0 { > compatible = "cache"; > + cache-level = <2>; > }; > > cluster1_l2_cache: l2-cache1 { > compatible = "cache"; > + cache-level = <2>; > }; > }; > > -- > 2.25.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel