linux-arm-kernel.lists.infradead.org archive mirror
 help / color / mirror / Atom feed
* [PATCH 1/3] arm64: dts: imx8mm: Deduplicate PCIe clock-names property
@ 2022-11-02 21:22 Marek Vasut
  2022-11-02 21:22 ` [PATCH 2/3] arm64: dts: imx8mp: " Marek Vasut
                   ` (3 more replies)
  0 siblings, 4 replies; 8+ messages in thread
From: Marek Vasut @ 2022-11-02 21:22 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Marek Vasut, Fabio Estevam, Peng Fan, Richard Zhu, Shawn Guo,
	NXP Linux Team

Move the PCIe clock-names property from various DTs into SoC dtsi to
reduce duplication. In case of a couple of boards, reorder the clock
so they match the order in yaml DT bindings.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: NXP Linux Team <linux-imx@nxp.com>
To: linux-arm-kernel@lists.infradead.org
---
 arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi  | 5 ++---
 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts | 5 ++---
 arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi               | 5 ++---
 arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi     | 1 -
 arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts | 6 +++---
 arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts   | 5 ++---
 arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi     | 5 ++---
 arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi     | 5 ++---
 arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi     | 5 ++---
 arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts      | 5 ++---
 arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts      | 5 ++---
 arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts      | 5 ++---
 arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts      | 5 ++---
 arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi            | 5 ++---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi                   | 1 +
 15 files changed, 28 insertions(+), 40 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
index 03266bd90a06b..f3cb7e27799e7 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
@@ -241,9 +241,8 @@ &pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
-	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-		 <&pcie0_refclk_gated>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk_gated>,
+		 <&clk IMX8MM_CLK_PCIE1_AUX>;
 	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
 	assigned-clock-rates = <10000000>, <250000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
index cd08430126887..a99cdb9630ef8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
@@ -905,9 +905,8 @@ &pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
-	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-		 <&pcieclk 0>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcieclk 0>,
+		 <&clk IMX8MM_CLK_PCIE1_AUX>;
 	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
 	assigned-clock-rates = <10000000>, <250000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
index 7d6317d95b131..7d004ffe7d4a6 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
@@ -358,9 +358,8 @@ &pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
-	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-		 <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+		 <&clk IMX8MM_CLK_PCIE1_AUX>;
 	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
 	assigned-clock-rates = <10000000>, <250000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
index 44e87b1568e79..1bbf1c1521415 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
@@ -212,7 +212,6 @@ &pcie0 {
 	reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>;
 	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_PHY>,
 		 <&clk IMX8MM_CLK_PCIE1_AUX>;
-	clock-names = "pcie", "pcie_bus", "pcie_aux";
 	fsl,max-link-speed = <1>;
 	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>;
 	assigned-clock-rates = <10000000>, <250000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
index 4a3df2b77b0be..4344d7b521911 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
@@ -175,9 +175,9 @@ &pcie0 {
 	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
 				 <&clk IMX8MM_SYS_PLL2_250M>;
 	assigned-clock-rates = <10000000>, <250000000>;
-	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-		 <&clk IMX8MM_CLK_PCIE1_PHY>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
+		 <&clk IMX8MM_CLK_PCIE1_PHY>,
+		 <&clk IMX8MM_CLK_PCIE1_AUX>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie>;
 	reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
index 7e0aeb2db3054..65b99e201d8f7 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
@@ -65,9 +65,8 @@ &pcie_phy {
 
 &pcie0 {
 	reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
-	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-		<&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+		 <&clk IMX8MM_CLK_PCIE1_AUX>;
 	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 				<&clk IMX8MM_CLK_PCIE1_CTRL>;
 	assigned-clock-rates = <10000000>, <250000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
index c557dbf4dcd60..0ce60ad9c7d50 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
@@ -120,9 +120,8 @@ &pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
-	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-		 <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+		 <&clk IMX8MM_CLK_PCIE1_AUX>;
 	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
 	assigned-clock-rates = <10000000>, <250000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
index 41d0de6a7027b..570992a52b759 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
@@ -142,9 +142,8 @@ &pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
-	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-		 <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+		 <&clk IMX8MM_CLK_PCIE1_AUX>;
 	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
 	assigned-clock-rates = <10000000>, <250000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
index 244ef8d6cc688..47ba0be554fa2 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
@@ -162,9 +162,8 @@ &pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
-	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-		 <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+		 <&clk IMX8MM_CLK_PCIE1_AUX>;
 	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
 	assigned-clock-rates = <10000000>, <250000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
index 750a1f07ecb7a..2bd117cefef84 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
@@ -702,9 +702,8 @@ &pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
-	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-		 <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+		 <&clk IMX8MM_CLK_PCIE1_AUX>;
 	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
 	assigned-clock-rates = <10000000>, <250000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
index 421fd0004eafc..3e203ace11da2 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
@@ -622,9 +622,8 @@ &pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
-	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-		 <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+		 <&clk IMX8MM_CLK_PCIE1_AUX>;
 	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
 	assigned-clock-rates = <10000000>, <250000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
index 8ce562246a08e..e7c79a82ab33d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
@@ -557,9 +557,8 @@ &pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
-	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-		 <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+		 <&clk IMX8MM_CLK_PCIE1_AUX>;
 	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
 	assigned-clock-rates = <10000000>, <250000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
index eceed9816f5dc..2c44ceefa6ae7 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
@@ -618,9 +618,8 @@ &pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
-	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-		 <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+		 <&clk IMX8MM_CLK_PCIE1_AUX>,
 	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
 	assigned-clock-rates = <10000000>, <250000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
index 0d454e0e2f7c8..ac7af722f240d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
@@ -654,9 +654,8 @@ &pcie0 {
 				 <&clk IMX8MM_SYS_PLL2_250M>;
 	assigned-clock-rates = <10000000>, <250000000>;
 	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
-		 <&clk IMX8MM_CLK_PCIE1_AUX>,
-		 <&clk IMX8MM_CLK_PCIE1_PHY>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
+		 <&clk IMX8MM_CLK_PCIE1_PHY>,
+		 <&clk IMX8MM_CLK_PCIE1_AUX>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie0>;
 	/* PCIE_1_RESET# (SODIMM 244) */
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index ac51ee6c28fe1..c11fcfc8e58dc 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1283,6 +1283,7 @@ pcie0: pcie@33800000 {
 					<0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 			fsl,max-link-speed = <2>;
 			linux,pci-domain = <0>;
+			clock-names = "pcie", "pcie_bus", "pcie_aux";
 			power-domains = <&pgc_pcie>;
 			resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
 				 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
-- 
2.35.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 8+ messages in thread
* [PATCH 2/3] arm64: dts: imx8mp: Deduplicate PCIe clock-names property
  2022-11-02 21:22 [PATCH 1/3] arm64: dts: imx8mm: Deduplicate PCIe clock-names property Marek Vasut
@ 2022-11-02 21:22 ` Marek Vasut
  2022-11-03  8:00   ` Alexander Stein
  2022-11-02 21:22 ` [PATCH 3/3] arm64: dts: imx8mq: " Marek Vasut
                   ` (2 subsequent siblings)
  3 siblings, 1 reply; 8+ messages in thread
From: Marek Vasut @ 2022-11-02 21:22 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Marek Vasut, Fabio Estevam, Peng Fan, Richard Zhu, Shawn Guo,
	NXP Linux Team

Move the PCIe clock-names property from various DTs into SoC dtsi to
reduce duplication. In case of a couple of boards, reorder the clock
so they match the order in yaml DT bindings.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: NXP Linux Team <linux-imx@nxp.com>
To: linux-arm-kernel@lists.infradead.org
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts           | 5 ++---
 arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts | 5 ++---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi              | 1 +
 3 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 9f1469db554d3..aa1cfa337c1ac 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -380,9 +380,8 @@ &pcie {
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
 	clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
-		 <&clk IMX8MP_CLK_PCIE_ROOT>,
-		 <&clk IMX8MP_CLK_HSIO_AXI>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
+		 <&clk IMX8MP_CLK_HSIO_AXI>,
+		 <&clk IMX8MP_CLK_PCIE_ROOT>;
 	assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
 	assigned-clock-rates = <10000000>;
 	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
index ceeca4966fc5c..8a8f2a7b7a5e8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
@@ -594,9 +594,8 @@ &pcie {
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>;
 	clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
-		 <&clk IMX8MP_CLK_PCIE_ROOT>,
-		 <&clk IMX8MP_CLK_HSIO_AXI>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
+		 <&clk IMX8MP_CLK_HSIO_AXI>,
+		 <&clk IMX8MP_CLK_PCIE_ROOT>;
 	assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
 	assigned-clock-rates = <10000000>;
 	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index d7039d9fe61ad..69f8b2a42528a 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -1192,6 +1192,7 @@ pcie: pcie@33800000 {
 					<0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 			fsl,max-link-speed = <3>;
 			linux,pci-domain = <0>;
+			clock-names = "pcie", "pcie_bus", "pcie_aux";
 			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
 			resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
 				 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
-- 
2.35.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 8+ messages in thread
* [PATCH 3/3] arm64: dts: imx8mq: Deduplicate PCIe clock-names property
  2022-11-02 21:22 [PATCH 1/3] arm64: dts: imx8mm: Deduplicate PCIe clock-names property Marek Vasut
  2022-11-02 21:22 ` [PATCH 2/3] arm64: dts: imx8mp: " Marek Vasut
@ 2022-11-02 21:22 ` Marek Vasut
  2022-11-03  7:56   ` Alexander Stein
  2022-11-03  7:58 ` [PATCH 1/3] arm64: dts: imx8mm: " Alexander Stein
  2022-11-11  6:33 ` Shawn Guo
  3 siblings, 1 reply; 8+ messages in thread
From: Marek Vasut @ 2022-11-02 21:22 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Marek Vasut, Fabio Estevam, Peng Fan, Richard Zhu, Shawn Guo,
	NXP Linux Team

Move the PCIe clock-names property from various DTs into SoC dtsi to
reduce duplication. In case of a couple of boards, reorder the clock
so they match the order in yaml DT bindings.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: NXP Linux Team <linux-imx@nxp.com>
To: linux-arm-kernel@lists.infradead.org
---
 arch/arm64/boot/dts/freescale/imx8mq-evk.dts           | 10 ++++------
 .../boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts   | 10 ++++------
 arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts   |  5 ++---
 .../arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts | 10 ++++------
 arch/arm64/boot/dts/freescale/imx8mq.dtsi              |  1 +
 5 files changed, 15 insertions(+), 21 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index 2102e9b57697c..0e095bb176c5f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -355,10 +355,9 @@ &pcie0 {
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
 	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
-		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
+		 <&pcie0_refclk>,
 		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
-		 <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+		 <&clk IMX8MQ_CLK_PCIE1_AUX>;
 	vph-supply = <&vgen5_reg>;
 	status = "okay";
 };
@@ -368,10 +367,9 @@ &pcie1 {
 	pinctrl-0 = <&pinctrl_pcie1>;
 	reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
 	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
-		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
+		 <&pcie0_refclk>,
 		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
-		 <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+		 <&clk IMX8MQ_CLK_PCIE2_AUX>;
 	vpcie-supply = <&reg_pcie1>;
 	vph-supply = <&vgen5_reg>;
 	status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
index a91c136797f60..6376417e918c2 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
@@ -245,20 +245,18 @@ &pcie0 {
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
 	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
-		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
+		 <&pcie0_refclk>,
 		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
-		 <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+		 <&clk IMX8MQ_CLK_PCIE1_AUX>;
 	status = "okay";
 };
 
 /* Intel Ethernet Controller I210/I211 */
 &pcie1 {
 	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
-		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
+		 <&pcie1_refclk>,
 		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
-		 <&pcie1_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+		 <&clk IMX8MQ_CLK_PCIE2_AUX>;
 	fsl,max-link-speed = <1>;
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
index 055031bba8c4b..200268660518d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
@@ -197,10 +197,9 @@ &pcie1 {
 	pinctrl-0 = <&pinctrl_pcie1>;
 	reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>;
 	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
-		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
+		 <&pcie1_refclk>,
 		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
-		 <&pcie1_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+		 <&clk IMX8MQ_CLK_PCIE2_AUX>;
 	status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts
index d7660eab68b94..344cfdaeb1d59 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts
@@ -105,10 +105,9 @@ &led2 {
 &pcie0 {
 	reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
 	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
-		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
+		 <&pcie0_refclk>,
 		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
-		 <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+		 <&clk IMX8MQ_CLK_PCIE1_AUX>;
 	epdev_on-supply = <&reg_vcc_3v3>;
 	hard-wired = <1>;
 	status = "okay";
@@ -120,10 +119,9 @@ &pcie0 {
  */
 &pcie1 {
 	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
-		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
+		 <&pcie1_refclk>,
 		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
-		 <&pcie1_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+		 <&clk IMX8MQ_CLK_PCIE2_AUX>;
 	epdev_on-supply = <&reg_vcc_3v3>;
 	hard-wired = <1>;
 	status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index c6530e5c7fef5..c47e2d7235d3e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1529,6 +1529,7 @@ pcie0: pcie@33800000 {
 			                <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 			fsl,max-link-speed = <2>;
 			linux,pci-domain = <0>;
+			clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
 			power-domains = <&pgc_pcie>;
 			resets = <&src IMX8MQ_RESET_PCIEPHY>,
 			         <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
-- 
2.35.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] arm64: dts: imx8mq: Deduplicate PCIe clock-names property
  2022-11-02 21:22 ` [PATCH 3/3] arm64: dts: imx8mq: " Marek Vasut
@ 2022-11-03  7:56   ` Alexander Stein
  0 siblings, 0 replies; 8+ messages in thread
From: Alexander Stein @ 2022-11-03  7:56 UTC (permalink / raw)
  To: linux-arm-kernel, Marek Vasut
  Cc: Fabio Estevam, Peng Fan, Richard Zhu, Shawn Guo, NXP Linux Team,
	Marek Vasut

Hi Marek,

Am Mittwoch, 2. November 2022, 22:22:48 CET schrieb Marek Vasut:
> Move the PCIe clock-names property from various DTs into SoC dtsi to
> reduce duplication. In case of a couple of boards, reorder the clock
> so they match the order in yaml DT bindings.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> To: linux-arm-kernel@lists.infradead.org
> ---
>  arch/arm64/boot/dts/freescale/imx8mq-evk.dts           | 10 ++++------
>  .../boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts   | 10 ++++------
>  arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts   |  5 ++---
>  .../arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts | 10 ++++------
>  arch/arm64/boot/dts/freescale/imx8mq.dtsi              |  1 +
>  5 files changed, 15 insertions(+), 21 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index
> 2102e9b57697c..0e095bb176c5f 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> @@ -355,10 +355,9 @@ &pcie0 {
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
>  	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
> -		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
> +		 <&pcie0_refclk>,
>  		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> +		 <&clk IMX8MQ_CLK_PCIE1_AUX>;
>  	vph-supply = <&vgen5_reg>;
>  	status = "okay";
>  };
> @@ -368,10 +367,9 @@ &pcie1 {
>  	pinctrl-0 = <&pinctrl_pcie1>;
>  	reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
>  	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
> -		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
> +		 <&pcie0_refclk>,
>  		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> +		 <&clk IMX8MQ_CLK_PCIE2_AUX>;
>  	vpcie-supply = <&reg_pcie1>;
>  	vph-supply = <&vgen5_reg>;
>  	status = "okay";
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
> b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts index
> a91c136797f60..6376417e918c2 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
> @@ -245,20 +245,18 @@ &pcie0 {
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
>  	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
> -		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
> +		 <&pcie0_refclk>,
>  		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> +		 <&clk IMX8MQ_CLK_PCIE1_AUX>;
>  	status = "okay";
>  };
> 
>  /* Intel Ethernet Controller I210/I211 */
>  &pcie1 {
>  	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
> -		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
> +		 <&pcie1_refclk>,
>  		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
> -		 <&pcie1_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> +		 <&clk IMX8MQ_CLK_PCIE2_AUX>;
>  	fsl,max-link-speed = <1>;
>  	status = "okay";
>  };
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
> b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts index
> 055031bba8c4b..200268660518d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
> @@ -197,10 +197,9 @@ &pcie1 {
>  	pinctrl-0 = <&pinctrl_pcie1>;
>  	reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>;
>  	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
> -		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
> +		 <&pcie1_refclk>,
>  		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
> -		 <&pcie1_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> +		 <&clk IMX8MQ_CLK_PCIE2_AUX>;
>  	status = "okay";
>  };
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts
> b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts index
> d7660eab68b94..344cfdaeb1d59 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts
> @@ -105,10 +105,9 @@ &led2 {
>  &pcie0 {
>  	reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
>  	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
> -		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
> +		 <&pcie0_refclk>,
>  		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> +		 <&clk IMX8MQ_CLK_PCIE1_AUX>;
>  	epdev_on-supply = <&reg_vcc_3v3>;
>  	hard-wired = <1>;
>  	status = "okay";
> @@ -120,10 +119,9 @@ &pcie0 {
>   */
>  &pcie1 {
>  	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
> -		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
> +		 <&pcie1_refclk>,
>  		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
> -		 <&pcie1_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> +		 <&clk IMX8MQ_CLK_PCIE2_AUX>;
>  	epdev_on-supply = <&reg_vcc_3v3>;
>  	hard-wired = <1>;
>  	status = "okay";
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index
> c6530e5c7fef5..c47e2d7235d3e 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -1529,6 +1529,7 @@ pcie0: pcie@33800000 {
>  			                <0 0 0 4 &gic GIC_SPI 122 
IRQ_TYPE_LEVEL_HIGH>;
>  			fsl,max-link-speed = <2>;
>  			linux,pci-domain = <0>;
> +			clock-names = "pcie", "pcie_bus", "pcie_phy", 
"pcie_aux";
>  			power-domains = <&pgc_pcie>;
>  			resets = <&src IMX8MQ_RESET_PCIEPHY>,
>  			         <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,

For imx8mq.dtsi and imx8mq-tqma8mq-mba8mx.dts:
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>

Thanks
Alexander




_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] arm64: dts: imx8mm: Deduplicate PCIe clock-names property
  2022-11-02 21:22 [PATCH 1/3] arm64: dts: imx8mm: Deduplicate PCIe clock-names property Marek Vasut
  2022-11-02 21:22 ` [PATCH 2/3] arm64: dts: imx8mp: " Marek Vasut
  2022-11-02 21:22 ` [PATCH 3/3] arm64: dts: imx8mq: " Marek Vasut
@ 2022-11-03  7:58 ` Alexander Stein
  2022-11-11  6:33 ` Shawn Guo
  3 siblings, 0 replies; 8+ messages in thread
From: Alexander Stein @ 2022-11-03  7:58 UTC (permalink / raw)
  To: linux-arm-kernel, Marek Vasut
  Cc: Fabio Estevam, Peng Fan, Richard Zhu, Shawn Guo, NXP Linux Team,
	Marek Vasut

Am Mittwoch, 2. November 2022, 22:22:46 CET schrieb Marek Vasut:
> Move the PCIe clock-names property from various DTs into SoC dtsi to
> reduce duplication. In case of a couple of boards, reorder the clock
> so they match the order in yaml DT bindings.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> To: linux-arm-kernel@lists.infradead.org
> ---
>  arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi  | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi               | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi     | 1 -
>  arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts | 6 +++---
>  arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts   | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi     | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi     | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi     | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts      | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts      | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts      | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts      | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi            | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi                   | 1 +
>  15 files changed, 28 insertions(+), 40 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi index
> 03266bd90a06b..f3cb7e27799e7 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
> @@ -241,9 +241,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcie0_refclk_gated>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk_gated>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
> b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts index
> cd08430126887..a99cdb9630ef8 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
> @@ -905,9 +905,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcieclk 0>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcieclk 0>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index
> 7d6317d95b131..7d004ffe7d4a6 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> @@ -358,9 +358,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi index
> 44e87b1568e79..1bbf1c1521415 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
> @@ -212,7 +212,6 @@ &pcie0 {
>  	reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>;
>  	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_PHY>,
>  		 <&clk IMX8MM_CLK_PCIE1_AUX>;
> -	clock-names = "pcie", "pcie_bus", "pcie_aux";
>  	fsl,max-link-speed = <1>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk
> IMX8MM_CLK_PCIE1_CTRL>; assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
> b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts index
> 4a3df2b77b0be..4344d7b521911 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
> @@ -175,9 +175,9 @@ &pcie0 {
>  	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
>  				 <&clk IMX8MM_SYS_PLL2_250M>;
>  	assigned-clock-rates = <10000000>, <250000000>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> -		 <&clk IMX8MM_CLK_PCIE1_PHY>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
> +		 <&clk IMX8MM_CLK_PCIE1_PHY>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie>;
>  	reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
> b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts index
> 7e0aeb2db3054..65b99e201d8f7 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
> @@ -65,9 +65,8 @@ &pcie_phy {
> 
>  &pcie0 {
>  	reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> -		<&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  				<&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi index
> c557dbf4dcd60..0ce60ad9c7d50 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
> @@ -120,9 +120,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi index
> 41d0de6a7027b..570992a52b759 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
> @@ -142,9 +142,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi index
> 244ef8d6cc688..47ba0be554fa2 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
> @@ -162,9 +162,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
> b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts index
> 750a1f07ecb7a..2bd117cefef84 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
> @@ -702,9 +702,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
> b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index
> 421fd0004eafc..3e203ace11da2 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
> @@ -622,9 +622,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
> b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts index
> 8ce562246a08e..e7c79a82ab33d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
> @@ -557,9 +557,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
> b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts index
> eceed9816f5dc..2c44ceefa6ae7 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
> @@ -618,9 +618,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>,
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index
> 0d454e0e2f7c8..ac7af722f240d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
> @@ -654,9 +654,8 @@ &pcie0 {
>  				 <&clk IMX8MM_SYS_PLL2_250M>;
>  	assigned-clock-rates = <10000000>, <250000000>;
>  	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
> -		 <&clk IMX8MM_CLK_PCIE1_AUX>,
> -		 <&clk IMX8MM_CLK_PCIE1_PHY>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +		 <&clk IMX8MM_CLK_PCIE1_PHY>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	/* PCIE_1_RESET# (SODIMM 244) */
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index
> ac51ee6c28fe1..c11fcfc8e58dc 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -1283,6 +1283,7 @@ pcie0: pcie@33800000 {
>  					<0 0 0 4 &gic GIC_SPI 122 
IRQ_TYPE_LEVEL_HIGH>;
>  			fsl,max-link-speed = <2>;
>  			linux,pci-domain = <0>;
> +			clock-names = "pcie", "pcie_bus", "pcie_aux";
>  			power-domains = <&pgc_pcie>;
>  			resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
>  				 <&src 
IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;

For imx8mm.dtsi and imx8mm-tqma8mqml-mba8mx.dts:
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>

Thanks
Alexander




_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 8+ messages in thread
* Re: [PATCH 2/3] arm64: dts: imx8mp: Deduplicate PCIe clock-names property
  2022-11-02 21:22 ` [PATCH 2/3] arm64: dts: imx8mp: " Marek Vasut
@ 2022-11-03  8:00   ` Alexander Stein
  0 siblings, 0 replies; 8+ messages in thread
From: Alexander Stein @ 2022-11-03  8:00 UTC (permalink / raw)
  To: linux-arm-kernel, Marek Vasut
  Cc: Fabio Estevam, Peng Fan, Richard Zhu, Shawn Guo, NXP Linux Team,
	Marek Vasut

Am Mittwoch, 2. November 2022, 22:22:47 CET schrieb Marek Vasut:
> Move the PCIe clock-names property from various DTs into SoC dtsi to
> reduce duplication. In case of a couple of boards, reorder the clock
> so they match the order in yaml DT bindings.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> To: linux-arm-kernel@lists.infradead.org
> ---
>  arch/arm64/boot/dts/freescale/imx8mp-evk.dts           | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mp.dtsi              | 1 +
>  3 files changed, 5 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index
> 9f1469db554d3..aa1cfa337c1ac 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> @@ -380,9 +380,8 @@ &pcie {
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
>  	clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> -		 <&clk IMX8MP_CLK_PCIE_ROOT>,
> -		 <&clk IMX8MP_CLK_HSIO_AXI>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +		 <&clk IMX8MP_CLK_HSIO_AXI>,
> +		 <&clk IMX8MP_CLK_PCIE_ROOT>;
>  	assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
>  	assigned-clock-rates = <10000000>;
>  	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
> b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts index
> ceeca4966fc5c..8a8f2a7b7a5e8 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
> @@ -594,9 +594,8 @@ &pcie {
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>;
>  	clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> -		 <&clk IMX8MP_CLK_PCIE_ROOT>,
> -		 <&clk IMX8MP_CLK_HSIO_AXI>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +		 <&clk IMX8MP_CLK_HSIO_AXI>,
> +		 <&clk IMX8MP_CLK_PCIE_ROOT>;
>  	assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
>  	assigned-clock-rates = <10000000>;
>  	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index
> d7039d9fe61ad..69f8b2a42528a 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -1192,6 +1192,7 @@ pcie: pcie@33800000 {
>  					<0 0 0 4 &gic GIC_SPI 123 
IRQ_TYPE_LEVEL_HIGH>;
>  			fsl,max-link-speed = <3>;
>  			linux,pci-domain = <0>;
> +			clock-names = "pcie", "pcie_bus", "pcie_aux";
>  			power-domains = <&hsio_blk_ctrl 
IMX8MP_HSIOBLK_PD_PCIE>;
>  			resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
>  				 <&src 
IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;

For imx8mp.dtsi:
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>

Thanks
Alexander



_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] arm64: dts: imx8mm: Deduplicate PCIe clock-names property
  2022-11-02 21:22 [PATCH 1/3] arm64: dts: imx8mm: Deduplicate PCIe clock-names property Marek Vasut
                   ` (2 preceding siblings ...)
  2022-11-03  7:58 ` [PATCH 1/3] arm64: dts: imx8mm: " Alexander Stein
@ 2022-11-11  6:33 ` Shawn Guo
  2022-11-11 14:03   ` Marek Vasut
  3 siblings, 1 reply; 8+ messages in thread
From: Shawn Guo @ 2022-11-11  6:33 UTC (permalink / raw)
  To: Marek Vasut
  Cc: linux-arm-kernel, Fabio Estevam, Peng Fan, Richard Zhu,
	NXP Linux Team

On Wed, Nov 02, 2022 at 10:22:46PM +0100, Marek Vasut wrote:
> Move the PCIe clock-names property from various DTs into SoC dtsi to
> reduce duplication. In case of a couple of boards, reorder the clock
> so they match the order in yaml DT bindings.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> To: linux-arm-kernel@lists.infradead.org
> ---
>  arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi  | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi               | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi     | 1 -
>  arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts | 6 +++---
>  arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts   | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi     | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi     | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi     | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts      | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts      | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts      | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts      | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi            | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi                   | 1 +
>  15 files changed, 28 insertions(+), 40 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
> index 03266bd90a06b..f3cb7e27799e7 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
> @@ -241,9 +241,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcie0_refclk_gated>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk_gated>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;

I'm not fond of it.  I would rather keep `clocks` and `clock-names`
appear as couple to ease the cross-checking.

Shawn

>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
> index cd08430126887..a99cdb9630ef8 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
> @@ -905,9 +905,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcieclk 0>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcieclk 0>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> index 7d6317d95b131..7d004ffe7d4a6 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> @@ -358,9 +358,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
> index 44e87b1568e79..1bbf1c1521415 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
> @@ -212,7 +212,6 @@ &pcie0 {
>  	reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>;
>  	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_PHY>,
>  		 <&clk IMX8MM_CLK_PCIE1_AUX>;
> -	clock-names = "pcie", "pcie_bus", "pcie_aux";
>  	fsl,max-link-speed = <1>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
> index 4a3df2b77b0be..4344d7b521911 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
> @@ -175,9 +175,9 @@ &pcie0 {
>  	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
>  				 <&clk IMX8MM_SYS_PLL2_250M>;
>  	assigned-clock-rates = <10000000>, <250000000>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> -		 <&clk IMX8MM_CLK_PCIE1_PHY>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
> +		 <&clk IMX8MM_CLK_PCIE1_PHY>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie>;
>  	reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
> index 7e0aeb2db3054..65b99e201d8f7 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
> @@ -65,9 +65,8 @@ &pcie_phy {
>  
>  &pcie0 {
>  	reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> -		<&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  				<&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
> index c557dbf4dcd60..0ce60ad9c7d50 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
> @@ -120,9 +120,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
> index 41d0de6a7027b..570992a52b759 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
> @@ -142,9 +142,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
> index 244ef8d6cc688..47ba0be554fa2 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
> @@ -162,9 +162,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
> index 750a1f07ecb7a..2bd117cefef84 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
> @@ -702,9 +702,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
> index 421fd0004eafc..3e203ace11da2 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
> @@ -622,9 +622,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
> index 8ce562246a08e..e7c79a82ab33d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
> @@ -557,9 +557,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
> index eceed9816f5dc..2c44ceefa6ae7 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
> @@ -618,9 +618,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>,
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
> index 0d454e0e2f7c8..ac7af722f240d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
> @@ -654,9 +654,8 @@ &pcie0 {
>  				 <&clk IMX8MM_SYS_PLL2_250M>;
>  	assigned-clock-rates = <10000000>, <250000000>;
>  	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
> -		 <&clk IMX8MM_CLK_PCIE1_AUX>,
> -		 <&clk IMX8MM_CLK_PCIE1_PHY>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +		 <&clk IMX8MM_CLK_PCIE1_PHY>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	/* PCIE_1_RESET# (SODIMM 244) */
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index ac51ee6c28fe1..c11fcfc8e58dc 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -1283,6 +1283,7 @@ pcie0: pcie@33800000 {
>  					<0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
>  			fsl,max-link-speed = <2>;
>  			linux,pci-domain = <0>;
> +			clock-names = "pcie", "pcie_bus", "pcie_aux";
>  			power-domains = <&pgc_pcie>;
>  			resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
>  				 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
> -- 
> 2.35.1
> 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] arm64: dts: imx8mm: Deduplicate PCIe clock-names property
  2022-11-11  6:33 ` Shawn Guo
@ 2022-11-11 14:03   ` Marek Vasut
  0 siblings, 0 replies; 8+ messages in thread
From: Marek Vasut @ 2022-11-11 14:03 UTC (permalink / raw)
  To: Shawn Guo
  Cc: linux-arm-kernel, Fabio Estevam, Peng Fan, Richard Zhu,
	NXP Linux Team

On 11/11/22 07:33, Shawn Guo wrote:
> On Wed, Nov 02, 2022 at 10:22:46PM +0100, Marek Vasut wrote:
>> Move the PCIe clock-names property from various DTs into SoC dtsi to
>> reduce duplication. In case of a couple of boards, reorder the clock
>> so they match the order in yaml DT bindings.
>>
>> Signed-off-by: Marek Vasut <marex@denx.de>
>> ---
>> Cc: Fabio Estevam <festevam@denx.de>
>> Cc: Peng Fan <peng.fan@nxp.com>
>> Cc: Richard Zhu <hongxing.zhu@nxp.com>
>> Cc: Shawn Guo <shawnguo@kernel.org>
>> Cc: NXP Linux Team <linux-imx@nxp.com>
>> To: linux-arm-kernel@lists.infradead.org
>> ---
>>   arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi  | 5 ++---
>>   arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts | 5 ++---
>>   arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi               | 5 ++---
>>   arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi     | 1 -
>>   arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts | 6 +++---
>>   arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts   | 5 ++---
>>   arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi     | 5 ++---
>>   arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi     | 5 ++---
>>   arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi     | 5 ++---
>>   arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts      | 5 ++---
>>   arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts      | 5 ++---
>>   arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts      | 5 ++---
>>   arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts      | 5 ++---
>>   arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi            | 5 ++---
>>   arch/arm64/boot/dts/freescale/imx8mm.dtsi                   | 1 +
>>   15 files changed, 28 insertions(+), 40 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
>> index 03266bd90a06b..f3cb7e27799e7 100644
>> --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
>> @@ -241,9 +241,8 @@ &pcie0 {
>>   	pinctrl-names = "default";
>>   	pinctrl-0 = <&pinctrl_pcie0>;
>>   	reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
>> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
>> -		 <&pcie0_refclk_gated>;
>> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
>> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk_gated>,
>> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
> 
> I'm not fond of it.  I would rather keep `clocks` and `clock-names`
> appear as couple to ease the cross-checking.

The downside of such mass duplication is the arbitrarily different 
ordering of clock/clock-names in some of those DTs, which needs to be 
corrected for dtbs_check validation to pass anyway. Since the 
clock-names are then identical across the SoC DTs, no need to duplicate 
that property anymore, one can simply open imx8m*.dtsi .

Note that there is a V2 of this series.

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-11-11 14:05 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-11-02 21:22 [PATCH 1/3] arm64: dts: imx8mm: Deduplicate PCIe clock-names property Marek Vasut
2022-11-02 21:22 ` [PATCH 2/3] arm64: dts: imx8mp: " Marek Vasut
2022-11-03  8:00   ` Alexander Stein
2022-11-02 21:22 ` [PATCH 3/3] arm64: dts: imx8mq: " Marek Vasut
2022-11-03  7:56   ` Alexander Stein
2022-11-03  7:58 ` [PATCH 1/3] arm64: dts: imx8mm: " Alexander Stein
2022-11-11  6:33 ` Shawn Guo
2022-11-11 14:03   ` Marek Vasut

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).