From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Shuah Khan <skhan@linuxfoundation.org>,
Shuah Khan <shuah@kernel.org>
Cc: Alan Hayward <alan.hayward@arm.com>,
Luis Machado <luis.machado@arm.com>,
Szabolcs Nagy <szabolcs.nagy@arm.com>,
linux-arm-kernel@lists.infradead.org,
linux-kselftest@vger.kernel.org, Mark Brown <broonie@kernel.org>
Subject: [PATCH v3 02/21] arm64: Document boot requirements for SME 2
Date: Fri, 11 Nov 2022 21:50:07 +0000 [thread overview]
Message-ID: <20221111215026.813348-3-broonie@kernel.org> (raw)
In-Reply-To: <20221111215026.813348-1-broonie@kernel.org>
SME 2 introduces the new ZT0 register, we require that access to this
reigster is not trapped when we identify that the feature is supported.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
Documentation/arm64/booting.rst | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst
index 8c324ad638de..81709132de7b 100644
--- a/Documentation/arm64/booting.rst
+++ b/Documentation/arm64/booting.rst
@@ -368,6 +368,16 @@ Before jumping into the kernel, the following conditions must be met:
- HCR_EL2.ATA (bit 56) must be initialised to 0b1.
+ For CPUs with the Scalable Matrix Extension version 2 (FEAT_SME2):
+
+ - If EL3 is present:
+
+ - SMCR_EL3.EZT0 (bit 30) must be initialised to 0b1.
+
+ - If the kernel is entered at EL1 and EL2 is present:
+
+ - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1.
+
The requirements described above for CPU mode, caches, MMUs, architected
timers, coherency and system registers apply to all CPUs. All CPUs must
enter the kernel in the same exception level. Where the values documented
--
2.30.2
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next prev parent reply other threads:[~2022-11-11 21:52 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-11 21:50 [PATCH v3 00/21] arm64/sme: Support SME 2 and SME 2.1 Mark Brown
2022-11-11 21:50 ` [PATCH v3 01/21] arm64/sme: Rename za_state to sme_state Mark Brown
2022-11-11 21:50 ` Mark Brown [this message]
2022-11-11 21:50 ` [PATCH v3 03/21] arm64/sysreg: Update system registers for SME 2 and 2.1 Mark Brown
2022-11-11 21:50 ` [PATCH v3 04/21] arm64/sme: Document SME 2 and SME 2.1 ABI Mark Brown
2022-11-11 21:50 ` [PATCH v3 05/21] arm64/esr: Document ISS for ZT0 being disabled Mark Brown
2022-11-11 21:50 ` [PATCH v3 06/21] arm64/sme: Manually encode ZT0 load and store instructions Mark Brown
2022-12-17 9:40 ` Zenghui Yu
2022-12-19 15:04 ` Mark Brown
2022-11-11 21:50 ` [PATCH v3 07/21] arm64/sme: Enable host kernel to access ZT0 Mark Brown
2022-11-11 21:50 ` [PATCH v3 08/21] arm64/sme: Add basic enumeration for SME2 Mark Brown
2022-11-11 21:50 ` [PATCH v3 09/21] arm64/sme: Provide storage for ZT0 Mark Brown
2022-12-17 9:28 ` Zenghui Yu
2022-11-11 21:50 ` [PATCH v3 10/21] arm64/sme: Implement context switching " Mark Brown
2022-11-11 21:50 ` [PATCH v3 11/21] arm64/sme: Implement signal handling for ZT Mark Brown
2022-11-11 21:50 ` [PATCH v3 12/21] arm64/sme: Implement ZT0 ptrace support Mark Brown
2022-12-17 9:23 ` Zenghui Yu
2022-11-11 21:50 ` [PATCH v3 13/21] arm64/sme: Add hwcaps for SME 2 and 2.1 features Mark Brown
2022-12-19 8:22 ` Zenghui Yu
2022-11-11 21:50 ` [PATCH v3 14/21] kselftest/arm64: Add a stress test program for ZT0 Mark Brown
2022-12-17 9:15 ` Zenghui Yu
2022-11-11 21:50 ` [PATCH v3 15/21] kselftest/arm64: Cover ZT in the FP stress test Mark Brown
2022-11-11 21:50 ` [PATCH v3 16/21] kselftest/arm64: Enumerate SME2 in the signal test utility code Mark Brown
2022-11-11 21:50 ` [PATCH v3 17/21] kselftest/arm64: Teach the generic signal context validation about ZT Mark Brown
2022-11-11 21:50 ` [PATCH v3 18/21] kselftest/arm64: Add test coverage for ZT register signal frames Mark Brown
2022-11-11 21:50 ` [PATCH v3 19/21] kselftest/arm64: Add SME2 coverage to syscall-abi Mark Brown
2022-11-11 21:50 ` [PATCH v3 20/21] kselftest/arm64: Add coverage of the ZT ptrace regset Mark Brown
2022-11-11 21:50 ` [PATCH v3 21/21] kselftest/arm64: Add coverage of SME 2 and 2.1 hwcaps Mark Brown
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