* [PATCH 2/3] dt-bindings: arm: fsl: Add an entry for Cloos PHG board
2022-11-13 12:44 [PATCH 1/3] dt-bindings: vendor-prefixes: Add an entry for Cloos Fabio Estevam
@ 2022-11-13 12:44 ` Fabio Estevam
2022-11-14 8:33 ` Krzysztof Kozlowski
2022-11-13 12:44 ` [PATCH 3/3] arm64: dts: imx8mm-phg: Add initial board support Fabio Estevam
` (2 subsequent siblings)
3 siblings, 1 reply; 6+ messages in thread
From: Fabio Estevam @ 2022-11-13 12:44 UTC (permalink / raw)
To: shawnguo
Cc: robh+dt, krzysztof.kozlowski+dt, devicetree, linux-arm-kernel,
Fabio Estevam
From: Fabio Estevam <festevam@denx.de>
Add an entry for the i.MX8MM Cloos PHG board.
Signed-off-by: Fabio Estevam <festevam@denx.de>
---
Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index f430eef712c8..05b5276a0e14 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -815,6 +815,7 @@ properties:
- enum:
- beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit
- boundary,imx8mm-nitrogen8mm # i.MX8MM Nitrogen Board
+ - cloos,imx8mm-phg # i.MX8MM Cloos PHG Board
- dmo,imx8mm-data-modul-edm-sbc # i.MX8MM eDM SBC
- emtrion,emcon-mx8mm-avari # emCON-MX8MM SoM on Avari Base
- fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board
--
2.25.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 3/3] arm64: dts: imx8mm-phg: Add initial board support
2022-11-13 12:44 [PATCH 1/3] dt-bindings: vendor-prefixes: Add an entry for Cloos Fabio Estevam
2022-11-13 12:44 ` [PATCH 2/3] dt-bindings: arm: fsl: Add an entry for Cloos PHG board Fabio Estevam
@ 2022-11-13 12:44 ` Fabio Estevam
2022-11-14 8:33 ` [PATCH 1/3] dt-bindings: vendor-prefixes: Add an entry for Cloos Krzysztof Kozlowski
2022-11-14 8:57 ` Shawn Guo
3 siblings, 0 replies; 6+ messages in thread
From: Fabio Estevam @ 2022-11-13 12:44 UTC (permalink / raw)
To: shawnguo
Cc: robh+dt, krzysztof.kozlowski+dt, devicetree, linux-arm-kernel,
Fabio Estevam
From: Fabio Estevam <festevam@denx.de>
Add the initial support for the i.MX8MM Cloos PHG board.
This board uses a imx8mm-tqma8mqml SoM from TQ-Group.
Signed-off-by: Fabio Estevam <festevam@denx.de>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
arch/arm64/boot/dts/freescale/imx8mm-phg.dts | 266 +++++++++++++++++++
2 files changed, 267 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-phg.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index c901404197c3..ef6f364eaa18 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -62,6 +62,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-bl.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-bl-osm-s.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-mx8menlo.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-phg.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-rdk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phg.dts b/arch/arm64/boot/dts/freescale/imx8mm-phg.dts
new file mode 100644
index 000000000000..e9447738b104
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-phg.dts
@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Fabio Estevam <festevam@denx.de>
+ */
+
+/dts-v1/;
+
+#include "imx8mm-tqma8mqml.dtsi"
+
+/ {
+ model = "Cloos i.MX8MM PHG board";
+ compatible = "cloos,imx8mm-phg", "tq,imx8mm-tqma8mqml", "fsl,imx8mm";
+
+ aliases {
+ mmc0 = &usdhc3;
+ mmc1 = &usdhc2;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ beeper {
+ compatible = "gpio-beeper";
+ pinctrl-0 = <&pinctrl_beeper>;
+ gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_led>;
+
+ led-0 {
+ label = "status1";
+ gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-1 {
+ label = "status2";
+ gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-2 {
+ label = "status3";
+ gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-3 {
+ label = "run";
+ gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-4 {
+ label = "powerled";
+ gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_otg_vbus_ctrl>;
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usdhc2_vmmc: regulator-vmmc {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <100>;
+ off-on-delay-us = <12000>;
+ };
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
+ compatible = "ethernet-phy-ieee802.3-c22";
+ };
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&usbphynop1 {
+ power-domains = <&pgc_otg1>;
+};
+
+&usbphynop2 {
+ power-domains = <&pgc_otg2>;
+};
+
+&usbotg1 {
+ dr_mode = "host";
+ vbus-supply = <®_usb_otg_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usdhc2 {
+ assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
+ assigned-clock-rates = <400000000>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ bus-width = <4>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ no-mmc;
+ no-sdio;
+ sd-uhs-sdr104;
+ sd-uhs-ddr50;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_beeper: beepergrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
+ MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
+ MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x40000002
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x40000002
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x14
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x14
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x14
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x14
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x14
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x14
+ MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x10
+ >;
+ };
+
+ pinctrl_gpio_led: gpioledgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19
+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19
+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
+ MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_otg_vbus_ctrl: otgvbusctrlgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x119
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ >;
+ };
+};
--
2.25.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 1/3] dt-bindings: vendor-prefixes: Add an entry for Cloos
2022-11-13 12:44 [PATCH 1/3] dt-bindings: vendor-prefixes: Add an entry for Cloos Fabio Estevam
2022-11-13 12:44 ` [PATCH 2/3] dt-bindings: arm: fsl: Add an entry for Cloos PHG board Fabio Estevam
2022-11-13 12:44 ` [PATCH 3/3] arm64: dts: imx8mm-phg: Add initial board support Fabio Estevam
@ 2022-11-14 8:33 ` Krzysztof Kozlowski
2022-11-14 8:57 ` Shawn Guo
3 siblings, 0 replies; 6+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-14 8:33 UTC (permalink / raw)
To: Fabio Estevam, shawnguo
Cc: robh+dt, krzysztof.kozlowski+dt, devicetree, linux-arm-kernel,
Fabio Estevam
On 13/11/2022 13:44, Fabio Estevam wrote:
> From: Fabio Estevam <festevam@denx.de>
>
> Carl Cloos Schweisstechnik GmbH develops, manufactures and delivers
> welding industrial solutions:
>
> https://www.cloos.de/de-en/
>
> Add a vendor prefix entry for it.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/3] dt-bindings: vendor-prefixes: Add an entry for Cloos
2022-11-13 12:44 [PATCH 1/3] dt-bindings: vendor-prefixes: Add an entry for Cloos Fabio Estevam
` (2 preceding siblings ...)
2022-11-14 8:33 ` [PATCH 1/3] dt-bindings: vendor-prefixes: Add an entry for Cloos Krzysztof Kozlowski
@ 2022-11-14 8:57 ` Shawn Guo
3 siblings, 0 replies; 6+ messages in thread
From: Shawn Guo @ 2022-11-14 8:57 UTC (permalink / raw)
To: Fabio Estevam
Cc: robh+dt, krzysztof.kozlowski+dt, devicetree, linux-arm-kernel,
Fabio Estevam
On Sun, Nov 13, 2022 at 09:44:57AM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <festevam@denx.de>
>
> Carl Cloos Schweisstechnik GmbH develops, manufactures and delivers
> welding industrial solutions:
>
> https://www.cloos.de/de-en/
>
> Add a vendor prefix entry for it.
>
> Signed-off-by: Fabio Estevam <festevam@denx.de>
Applied all, thanks!
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^ permalink raw reply [flat|nested] 6+ messages in thread