From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C01CCC433FE for ; Mon, 14 Nov 2022 01:59:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=K5+f+o5uNC5zuhPM+vDsyudaZgc+DXwcWN+IMS/tg2Y=; b=wDKvmLM/VzU7NO eic2Dcq3q9Ho//whU0KiCtTmhr6jEgZMt+eytJpFx38hvnU2z3k3mN35BfJ3HXdMqCcnuF1BpR21P DA0VbLCg3C8vUAx0itGZ27CGfhbXCqwThOb5Yv502mfDyY08tgXC+QrdVszELQINXlUdehbsEF4Q5 wy/8A2dA3FHisX0Tgl1nIP9Rt+PLGhVhQMyrcKO4IHSbtClUjmmRjyWD1DQGr1/4Q7iPFA3TUECsX csBIMFjs5EqX4/Dx/0QDIBqxwxnuCXc1fQyTD/BobiqMBRm741lnLfz3OdnH4nukG9ZiyKkHJvtRK g7UzXa5Ra5uktw0OQOCQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ouOk5-00FUUf-Ej; Mon, 14 Nov 2022 01:58:33 +0000 Received: from wout2-smtp.messagingengine.com ([64.147.123.25]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ouOjc-00FUMQ-4G for linux-arm-kernel@lists.infradead.org; Mon, 14 Nov 2022 01:58:06 +0000 Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.west.internal (Postfix) with ESMTP id ACDC8320091A; Sun, 13 Nov 2022 20:57:57 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute5.internal (MEProxy); Sun, 13 Nov 2022 20:57:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm2; t=1668391077; x=1668477477; bh=zX +HYuy4GvidniLAd+lpqew4/s4ii686Qj3H9Jd2qG0=; b=rXsRbMYFTaUdR2U+Mk VNvxUrkjZXlEk44QuPfO3v95apqzkYDbTcuAIKi3cFSmP1R5I36syDaXMzUiRXV5 ZUG23SwDwoYqTOgIQt7vg0VHxW/GFVMDFVeoQSX5WU3iAAln+nsR8Q5Bni10xOaX B9M+OAK5vMjbNdi7pRHiBVwVvw7y1j0WyajuPvNXe7Zz4PPjTQEaLOnmvpLChWLW 5Qk/M3W2QI0t99TuVFL04WYT5ysYIs4q5r/B1QuF3lVUzgOjhm3yJoFDmy1aepYi jVupkZ6508nbFlesKkfDqFbbhzMzUE3O6HnCuo3dGPf7m1foGPbVFgxwxm4j0ana TIqw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :feedback-id:feedback-id:from:from:in-reply-to:in-reply-to :message-id:mime-version:references:reply-to:sender:subject :subject:to:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; t=1668391077; x=1668477477; bh=zX+HYuy4Gvidn iLAd+lpqew4/s4ii686Qj3H9Jd2qG0=; b=MH1Dg8+TQL2ERs5dtT00JLdXcQfB6 c2fJd7iyyNYKiV/keuHUtO6s2q1mAAs6HS9VQfpUKkBh/fzKgWvN3c3XMfGqpLoX IQqwXXVRlCKH08XEQswZG0lmo8pkgPjSYIa6qxzlanDSmxgWxSE1bVCDRvj0Ya/j NCtIEjGEjLozLrclr0QJIcrAPF9XoQjw+Z3YTnPiOmjimezhLNMWUalzf7c1jF/o G6jTQOKLHpk2TEMvbpSxskt+xPzUJbh5Ri0sfmfdMOmUSGyTQlbqSloJo1lL7MQ/ l6OFLXUZTm1jtwlWJwRzZFyvTgu19aeGBsM+ciohTPYAFEQrIpP6ClF1w== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvgedrgedugdegtdcutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvfevufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpefurghmuhgv lhcujfholhhlrghnugcuoehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhgqeenucggtf frrghtthgvrhhnpedukeetueduhedtleetvefguddvvdejhfefudelgfduveeggeehgfdu feeitdevteenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhroh hmpehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhg X-ME-Proxy: Feedback-ID: i0ad843c9:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sun, 13 Nov 2022 20:57:56 -0500 (EST) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec Cc: Ivaylo Dimitrov , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, Andre Przywara , Samuel Holland Subject: [PATCH v3 3/3] bus: sunxi-rsb: Clear interrupt status before each transfer Date: Sun, 13 Nov 2022 19:57:49 -0600 Message-Id: <20221114015749.28490-4-samuel@sholland.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221114015749.28490-1-samuel@sholland.org> References: <20221114015749.28490-1-samuel@sholland.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221113_175804_238681_EEE3519F X-CRM114-Status: GOOD ( 14.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Currently, the driver clears the interrupt status bits after anything could have set them. However, this requires duplicating the same logic in several places. Instead of clearing the status flags in the interrupt handler, disable all further interrupts by clearing the RSB_CTRL_GLOBAL_INT_ENB bit. Then we can delay the status register write until the start of the next transfer, so it only has to be done in one place. Signed-off-by: Samuel Holland --- Changes in v3: - Add a patch refactoring how the status bits are cleared drivers/bus/sunxi-rsb.c | 20 +++++--------------- 1 file changed, 5 insertions(+), 15 deletions(-) diff --git a/drivers/bus/sunxi-rsb.c b/drivers/bus/sunxi-rsb.c index 3aa91aed3bf7..cb622e60897b 100644 --- a/drivers/bus/sunxi-rsb.c +++ b/drivers/bus/sunxi-rsb.c @@ -279,6 +279,7 @@ static int _sunxi_rsb_run_xfer(struct sunxi_rsb *rsb) int_mask = RSB_INTS_LOAD_BSY | RSB_INTS_TRANS_ERR | RSB_INTS_TRANS_OVER; writel(int_mask, rsb->regs + RSB_INTE); + writel(int_mask, rsb->regs + RSB_INTS); writel(RSB_CTRL_START_TRANS | RSB_CTRL_GLOBAL_INT_ENB, rsb->regs + RSB_CTRL); @@ -286,7 +287,6 @@ static int _sunxi_rsb_run_xfer(struct sunxi_rsb *rsb) timeout = readl_poll_timeout_atomic(rsb->regs + RSB_INTS, status, (status & int_mask), 10, 100000); - writel(status, rsb->regs + RSB_INTS); } else { timeout = !wait_for_completion_io_timeout(&rsb->complete, msecs_to_jiffies(100)); @@ -296,12 +296,9 @@ static int _sunxi_rsb_run_xfer(struct sunxi_rsb *rsb) if (timeout) { dev_dbg(rsb->dev, "RSB timeout\n"); - /* abort the transfer */ + /* abort the transfer and disable interrupts */ writel(RSB_CTRL_ABORT_TRANS, rsb->regs + RSB_CTRL); - /* clear any interrupt flags */ - writel(readl(rsb->regs + RSB_INTS), rsb->regs + RSB_INTS); - return -ETIMEDOUT; } @@ -503,15 +500,11 @@ EXPORT_SYMBOL_GPL(__devm_regmap_init_sunxi_rsb); static irqreturn_t sunxi_rsb_irq(int irq, void *dev_id) { struct sunxi_rsb *rsb = dev_id; - u32 status; - status = readl(rsb->regs + RSB_INTS); - rsb->status = status; + /* disable interrupts */ + writel(0, rsb->regs + RSB_CTRL); - /* Clear interrupts */ - status &= (RSB_INTS_LOAD_BSY | RSB_INTS_TRANS_ERR | - RSB_INTS_TRANS_OVER); - writel(status, rsb->regs + RSB_INTS); + rsb->status = readl(rsb->regs + RSB_INTS); complete(&rsb->complete); @@ -532,9 +525,6 @@ static int sunxi_rsb_init_device_mode(struct sunxi_rsb *rsb) if (reg & RSB_DMCR_DEVICE_START) ret = -ETIMEDOUT; - /* clear interrupt status bits */ - writel(readl(rsb->regs + RSB_INTS), rsb->regs + RSB_INTS); - return ret; } -- 2.37.3 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel