[PATCH] arm64: mm: Align PGDs to at least 64 bytes

[Ard Biesheuvel <ardb@kernel.org>]

My copy of the ARM ARM (DDI 0487G.a) no longer describes the 64 byte
minimum alignment of root page tables as being conditional on whether
52-bit physical addressing is supported and enabled, even though I seem
to remember that this was the case formerly (and our code suggests the
same).

So align pgd_t[] allocations to 64 bytes. Note that this only affects
16k/4 levels configurations, which are unlikely to be in wide use.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
---
 arch/arm64/mm/pgd.c | 13 +++----------
 1 file changed, 3 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/mm/pgd.c b/arch/arm64/mm/pgd.c
index 4a64089e5771c1e2..8f01a75c35caaa9a 100644
--- a/arch/arm64/mm/pgd.c
+++ b/arch/arm64/mm/pgd.c
@@ -40,17 +40,10 @@ void __init pgtable_cache_init(void)
 	if (PGD_SIZE == PAGE_SIZE)
 		return;
 
-#ifdef CONFIG_ARM64_PA_BITS_52
 	/*
-	 * With 52-bit physical addresses, the architecture requires the
-	 * top-level table to be aligned to at least 64 bytes.
+	 * Naturally aligned pgds required by the architecture, with a minimum
+	 * alignment of 64 bytes.
 	 */
-	BUILD_BUG_ON(PGD_SIZE < 64);
-#endif
-
-	/*
-	 * Naturally aligned pgds required by the architecture.
-	 */
-	pgd_cache = kmem_cache_create("pgd_cache", PGD_SIZE, PGD_SIZE,
+	pgd_cache = kmem_cache_create("pgd_cache", PGD_SIZE, max(PGD_SIZE, 64),
 				      SLAB_PANIC, NULL);
 }
-- 
2.35.1


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