From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9C27FC4332F for ; Thu, 15 Dec 2022 17:55:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:CC:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=3hjgf8pvDgZs2XTLSBsSALcXV3wPogg+fQBAFhK2Nis=; b=FXcKVUiriR4bdi J6yJMKFtU63V+pU5iQqVd8nO0b/UZz95u1r3gAE3jSXYrrgtGlNQTpisMhhpMkGu5cgED76qKvFBd 7sQ3vRgcRqugrUUjHTaitOWnzpSSp1vIpsKWAWiuvVzk+rZer8UI3as8KAyLg/zBGrkq06ySdClE2 XZuyeyWFkM5h/JqNXx2lkOq9raGKWea6qXlen0BvTFxXf6mV0IGSgwvTA1Dlf9G1GQye8j0aA8CVD 4q/Dq/1SH4mrZP9tsLKmi9Ms6ho1Zxil1pFUrbOZ/D41+eDe859EYZ2AvQQJExWZ5wo9CQwPUKJ7u ihxaMzM5iI+QqyKjq64A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p5sRM-00Aj62-13; Thu, 15 Dec 2022 17:54:40 +0000 Received: from lelv0142.ext.ti.com ([198.47.23.249]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1p5sRI-00Aj4H-T7 for linux-arm-kernel@lists.infradead.org; Thu, 15 Dec 2022 17:54:38 +0000 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2BFHsBIh074336; Thu, 15 Dec 2022 11:54:11 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1671126851; bh=dfl4riunx9/vsckoIqhbcncF2BLRdYLcE2m8tUkN8lM=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=wCDRsX4gv7j/zhhzpUZUO9M7Ft1Pqlt7O5z9HdWYDyDF5Xtj1fYqjC8tX0PZ7uID+ AkRadICMYbN35T+4kT0M+fZEYLUWw0FB6RrAwCze0vJEhxhOoyAz3j6u1PuABVdPwy dHmcdDrmNVUT7OMbAzgmO95FFBMMzxbTxdtENTSU= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2BFHsBS2015667 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 15 Dec 2022 11:54:11 -0600 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Thu, 15 Dec 2022 11:54:11 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Thu, 15 Dec 2022 11:54:11 -0600 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2BFHsBMg067845; Thu, 15 Dec 2022 11:54:11 -0600 Date: Thu, 15 Dec 2022 11:54:11 -0600 From: Nishanth Menon To: Mark Brown CC: jerome Neanne , Wadim Egorov , "lgirdwood@gmail.com" , "robh+dt@kernel.org" , "kristo@kernel.org" , "dmitry.torokhov@gmail.com" , "krzysztof.kozlowski+dt@linaro.org" , "catalin.marinas@arm.com" , "will@kernel.org" , "lee@kernel.org" , "tony@atomide.com" , "vigneshr@ti.com" , "shawnguo@kernel.org" , "geert+renesas@glider.be" , "dmitry.baryshkov@linaro.org" , "marcel.ziswiler@toradex.com" , "vkoul@kernel.org" , "biju.das.jz@bp.renesas.com" , "arnd@arndb.de" , "jeff@labundy.com" , "afd@ti.com" , "khilman@baylibre.com" , "narmstrong@baylibre.com" , "msp@baylibre.com" , "j-keerthy@ti.com" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-input@vger.kernel.org" , "linux-omap@vger.kernel.org" Subject: Re: [PATCH v7 1/6] DONOTMERGE: arm64: dts: ti: Add TI TPS65219 PMIC support for AM642 SK board. Message-ID: <20221215175411.znxy3d6ussq2iq5h@grieving> References: <20221104152311.1098603-1-jneanne@baylibre.com> <20221104152311.1098603-2-jneanne@baylibre.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20171215 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221215_095437_128971_86ED0D8B X-CRM114-Status: GOOD ( 20.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 16:09-20221215, Mark Brown wrote: > On Thu, Dec 15, 2022 at 04:51:40PM +0100, jerome Neanne wrote: > > On 15/12/2022 16:09, Wadim Egorov wrote: > = > > > I am testing your PMIC patches on a AM62 based board with a similar s= etup and > > > running into the following error > = > > > =A0=A0 VDDSHV5_SDIO: bypassed regulator has no supply! > > > =A0=A0 VDDSHV5_SDIO: will resolve supply early: ldo1 > > > =A0=A0 VDDSHV5_SDIO: supplied by regulator-dummy > > > =A0=A0 VDDSHV5_SDIO: failed to get the current voltage: -EINVAL > = > > > Have you noticed problems with LDO1 and bypass mode? > = > > I did not noticed this on am642 board but IIRC this rail was not used. I > > heard about similar issue reported to me by Nishanth M with a fix propo= sal > > here: > > https://gist.github.com/nmenon/e4dd6ef6afe31bc9750fa6cbee8d3e25 > = > That proposal looks really non-idiomatic and quite unusual, if there's a > fixed voltage supply to the LDO I'd expect to see it modeled as a fixed > voltage regulator. I'm not sure what the use of bypass here is trying > to accomplish TBH. Correct - My hack was based on a time crunch hack ;)... The problem is this - the default NVM in the PMIC is setup such that VSET value =3D3.3v and bypass bit set (makes sense since the vin=3D3.3v). Now the constraint is bypass bit cannot be changed without the LDO being switched off. regulator-allow-bypass property allows us to control bypass bit, but we should'nt toggle it when LDO is active. Not providing the property implies the bit wont be toggled by regulator core either. What we need is a scheme that will disable the bypass bit with the intent of operating the LDO with just the vset field. I did'nt find it possible atm.. unless I am mistaken.. -- = Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5= 849D 1736 249D _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel