From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 694AAC3DA7A for ; Sat, 31 Dec 2022 13:36:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=wbXg4pGV5gzh/2e8OmxgM4ir0QXfMBNeUvQi3b1rx0Q=; b=SSnnACiq1ok4RH 8VoruSwbD80G5e9cy+NuuwMOjQUA32QwG8Ba1z2Liaeo4/Hk/STrgLu9iETLFCnq8n2CenrZdOTaS +HXWVDUJbLJAOeXx603cZs6zlqWdsPJvAAHdSh6tb4lzjzHU07DGIyRm0a59mCQBPZUbKYmwLq1+z rRDipdNKQ1KI6W0BcuBPCJRla4sl7XqzT6xPkWqGvU4CeF1C9jVVsaefyCUn3dkD2yo47DlFW6DmM rFLr1VMA5s3H6v5Hr1Ecpmq1nb7k5d+g/ghXSgbBqno+9fL4Wf8wDBMuMQ0ytcUJ0mfoNzMoUiUNH 2gRLmbHwK4oMmU+ha5Qw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pBc11-005rgJ-Nz; Sat, 31 Dec 2022 13:35:11 +0000 Received: from ams.source.kernel.org ([145.40.68.75]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pBc0w-005rdz-KI for linux-arm-kernel@lists.infradead.org; Sat, 31 Dec 2022 13:35:09 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id D9078B8075A; Sat, 31 Dec 2022 13:35:04 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A23F6C433EF; Sat, 31 Dec 2022 13:35:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1672493703; bh=dUnijUHbgerYaBzn9Rg23kVSkLXe70+EE1pNnR1zUuw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=cHSEUqYKnvGPlARWi/AMAcNkhRPToDn/GslN7uuW7RCqWuaQYIkinrbZS7FQZnSNg KJvdsv/d106SjzhUn94GO+7gkl7XeUUKYTbOzvZSPF06l6vyeVVFrjnUB83YnlxbJ7 0QgKMIrjv9W/IgRGE3h6V1Jica9hfh4tquR+7iH092UQEBdqprp1cLxtc6mJiqmx7B pnauiV8ZT94c4SdYOgdZs4EMBN22OtSuiFEOOdWKOetoRrL3sQxGQ9h44j+WSwvjAk muZa1FADl9+FohPmFi2kYrMf9QUU0BVWMJFaVdq3WeHi2Vz0CBtbKcFOdgExKpe6jP AhHJtzDcCQ4IA== Date: Sat, 31 Dec 2022 21:34:55 +0800 From: Shawn Guo To: Vladimir Oltean Cc: devicetree@vger.kernel.org, iommu@lists.linux.dev, Laurentiu Tudor , Will Deacon , Robin Murphy , linux-arm-kernel@lists.infradead.org, Li Yang , Rob Herring , Krzysztof Kozlowski , linux-kernel@vger.kernel.org, Michael Walle Subject: Re: [PATCH v2 1/2] arm64: dts: ls1028a: declare cache-coherent page table walk feature for IOMMU Message-ID: <20221231133454.GF6112@T480> References: <20221215135636.3684026-1-vladimir.oltean@nxp.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221215135636.3684026-1-vladimir.oltean@nxp.com> User-Agent: Mutt/1.9.4 (2018-02-28) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221231_053508_158434_EDD0F216 X-CRM114-Status: GOOD ( 14.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Dec 15, 2022 at 03:56:35PM +0200, Vladimir Oltean wrote: > The SMMUv2 driver for MMU-500 reads the ARM_SMMU_GR0_ID0 register at > probe time and tries to determine based on the CTTW (Coherent > Translation Table Walk) bit whether this feature is supported. > > Unfortunately, it looks like the SMMU integration in the NXP LS1028A has > wrongly tied the cfg_cttw signal to 0, even though the SoC documentation > specifies that "The SMMU supports cache coherency for page table walks > and DVM transactions for page table cache maintenance operations." > > Device tree provides the option of overriding the ID register via the > dma-coherent property since commit bae2c2d421cd ("iommu/arm-smmu: Sort > out coherency"), and that's what we do here. > > Telling struct io_pgtable_cfg that the SMMU page table walks are > coherent with the CPU caches brings performance benefits, because it > avoids certain operations such as __arm_lpae_sync_pte() for PTE updates. > > Link: https://lore.kernel.org/linux-iommu/3f3112e4-65ff-105d-8cd7-60495ec9054a@arm.com/ > Suggested-by: Robin Murphy > Signed-off-by: Vladimir Oltean Applied both, thanks! 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