From: Samuel Holland <samuel@sholland.org>
To: Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: "Samuel Holland" <samuel@sholland.org>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
"Rob Herring" <robh+dt@kernel.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-sunxi@lists.linux.dev,
"András Szemző" <szemzo.andras@gmail.com>,
"Andre Przywara" <andre.przywara@arm.com>
Subject: [PATCH v2 4/6] clk: sunxi-ng: d1: Mark cpux clock as critical
Date: Sat, 31 Dec 2022 17:14:27 -0600 [thread overview]
Message-ID: <20221231231429.18357-5-samuel@sholland.org> (raw)
In-Reply-To: <20221231231429.18357-1-samuel@sholland.org>
From: András Szemző <szemzo.andras@gmail.com>
Some SoCs in the D1 family feature ARM CPUs instead of a RISC-V CPU.
In that case, the CPUs are driven from the 'cpux' clock, so it needs
to be marked as critical, since there is no consumer when DVFS is
disabled. This matches the drivers for other SoCs, and the "riscv"
clock in this driver.
Signed-off-by: András Szemző <szemzo.andras@gmail.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
Changes in v2:
- Expand commit message
drivers/clk/sunxi-ng/ccu-sun20i-d1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun20i-d1.c b/drivers/clk/sunxi-ng/ccu-sun20i-d1.c
index 8ef3cdeb7962..c5a7df93602c 100644
--- a/drivers/clk/sunxi-ng/ccu-sun20i-d1.c
+++ b/drivers/clk/sunxi-ng/ccu-sun20i-d1.c
@@ -240,7 +240,7 @@ static const struct clk_parent_data cpux_parents[] = {
{ .hw = &pll_periph0_800M_clk.common.hw },
};
static SUNXI_CCU_MUX_DATA(cpux_clk, "cpux", cpux_parents,
- 0x500, 24, 3, CLK_SET_RATE_PARENT);
+ 0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
static const struct clk_hw *cpux_hws[] = { &cpux_clk.common.hw };
static SUNXI_CCU_M_HWS(cpux_axi_clk, "cpux-axi",
--
2.37.4
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next prev parent reply other threads:[~2022-12-31 23:17 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-31 23:14 [PATCH v2 0/6] clk: sunxi-ng: Allwinner R528/T113 clock support Samuel Holland
2022-12-31 23:14 ` [PATCH v2 1/6] clk: sunxi-ng: Remove duplicate ARCH_SUNXI dependencies Samuel Holland
2022-12-31 23:14 ` [PATCH v2 2/6] clk: sunxi-ng: Move SoC driver conditions to dependencies Samuel Holland
2022-12-31 23:14 ` [PATCH v2 3/6] clk: sunxi-ng: d1: Allow building for R528/T113 Samuel Holland
2022-12-31 23:14 ` Samuel Holland [this message]
2022-12-31 23:14 ` [PATCH v2 5/6] dt-bindings: clock: Add D1 CAN bus gates and resets Samuel Holland
2023-01-01 15:38 ` Krzysztof Kozlowski
2023-01-02 15:23 ` Philipp Zabel
2022-12-31 23:14 ` [PATCH v2 6/6] clk: sunxi-ng: d1: Add " Samuel Holland
2023-01-05 17:34 ` Jernej Škrabec
2023-01-08 21:06 ` [PATCH v2 0/6] clk: sunxi-ng: Allwinner R528/T113 clock support Jernej Škrabec
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