From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5BB2AC54E94 for ; Thu, 26 Jan 2023 13:40:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=taxEtcLpS//3tb7PhiDksw6eVBFVldnnDyqy8A6n+sw=; b=zGzkYyvjRtqVnJ ZAcp6ulfC+TqHINJTgl0sd9mfsqWxA5iTgn3qHfsHQOU4wl3nbWOuOwRbtn9b2JloymJtqelOnZNl JNKh+jXmk6855nQNWNL/zir8nntkVph/i+oOUWah1mrJA/mQ2GJA+qC79jvf31ncPaqlixR07eXyl 4vUNBUDn2fz+LcBRDNcbbqfBUkZiLKDoX50l1lbZ6WATmSsyts0U/gAeR/sCLuS14tBJkHlqqnrue bU6Z/XNN9GIDQ5vPeqK7wW1/sHqmXyIMDlZnlOXUo47W+i6clSTs6SEPoU4NAzj/1xTNYmdwGfPdw FE1IwmFF733hgJkNKHLg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pL2Tc-00AyOt-IC; Thu, 26 Jan 2023 13:39:40 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pL2TZ-00AyNn-9Z for linux-arm-kernel@lists.infradead.org; Thu, 26 Jan 2023 13:39:39 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 9FC69617D6; Thu, 26 Jan 2023 13:39:36 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3F00CC4339C; Thu, 26 Jan 2023 13:39:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1674740376; bh=JubJEGHP7L4BLz+Yv107k+IilgVcrBBFP6L7DrL83Qw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=hfeuHN+xYiDzBOd1yd65YRHWnHAlwdILwlugc9bJFSxFmDausavMiu5CGyHWc8aub HWgASUXP3tnSVApnsLCjJ8LskitebU1QB+3W2PbZPbi7Yle/BZ/fgU+k+rddLAk9vT E6spsE/p2l4HrRbEhn3damJrxHQne/o0wbAMCK8GsyuOBr/Rh3z4+AkPTOmWDrVuv5 emffqnkhgty65XVwGrdS5sfHl9U4IIvAPcBs1HFr2KmSimoOSbbyHCi9nZU3nG+8cD L5InkY4tXsu/QaKG/iP7Caxphgn137B6tEdHWefzBK6z0LrPIrWoJ/PM7LlLAa2hmS CtnJtcIIWTsPQ== Date: Thu, 26 Jan 2023 13:39:30 +0000 From: Will Deacon To: Sumit Garg Cc: catalin.marinas@arm.com, mark.rutland@arm.com, daniel.thompson@linaro.org, dianders@chromium.org, liwei391@huawei.com, mhiramat@kernel.org, maz@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v5 1/2] arm64: entry: Skip single stepping into interrupt handlers Message-ID: <20230126133929.GC29148@willie-the-truck> References: <20221219102452.2860088-1-sumit.garg@linaro.org> <20221219102452.2860088-2-sumit.garg@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221219102452.2860088-2-sumit.garg@linaro.org> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230126_053937_429086_94C82D05 X-CRM114-Status: GOOD ( 28.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Dec 19, 2022 at 03:54:51PM +0530, Sumit Garg wrote: > Currently on systems where the timer interrupt (or any other > fast-at-human-scale periodic interrupt) is active then it is impossible > to step any code with interrupts unlocked because we will always end up > stepping into the timer interrupt instead of stepping the user code. > > The common user's goal while single stepping is that when they step then > the system will stop at PC+4 or PC+I for a branch that gets taken > relative to the instruction they are stepping. So, fix broken single step > implementation via skipping single stepping into interrupt handlers. > > The methodology is when we receive an interrupt from EL1, check if we > are single stepping (pstate.SS). If yes then we save MDSCR_EL1.SS and > clear the register bit if it was set. Then unmask only D and leave I set. > On return from the interrupt, set D and restore MDSCR_EL1.SS. Along with > this skip reschedule if we were stepping. > > Suggested-by: Will Deacon > Signed-off-by: Sumit Garg > Tested-by: Douglas Anderson > --- > arch/arm64/kernel/entry-common.c | 22 ++++++++++++++++++++-- > 1 file changed, 20 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c > index cce1167199e3..688d1ef8e864 100644 > --- a/arch/arm64/kernel/entry-common.c > +++ b/arch/arm64/kernel/entry-common.c > @@ -231,11 +231,15 @@ DEFINE_STATIC_KEY_TRUE(sk_dynamic_irqentry_exit_cond_resched); > #define need_irq_preemption() (IS_ENABLED(CONFIG_PREEMPTION)) > #endif > > -static void __sched arm64_preempt_schedule_irq(void) > +static void __sched arm64_preempt_schedule_irq(struct pt_regs *regs) > { > if (!need_irq_preemption()) > return; > > + /* Don't reschedule in case we are single stepping */ > + if (!(regs->pstate & DBG_SPSR_SS)) > + return; Hmm, isn't this the common case? PSTATE.SS will usually be clear, no? > * Note: thread_info::preempt_count includes both thread_info::count > * and thread_info::need_resched, and is not equivalent to > @@ -471,19 +475,33 @@ static __always_inline void __el1_irq(struct pt_regs *regs, > do_interrupt_handler(regs, handler); > irq_exit_rcu(); > > - arm64_preempt_schedule_irq(); > + arm64_preempt_schedule_irq(regs); > > exit_to_kernel_mode(regs); > } > + > static void noinstr el1_interrupt(struct pt_regs *regs, > void (*handler)(struct pt_regs *)) > { > + unsigned long mdscr; > + > + /* Disable single stepping within interrupt handler */ > + if (regs->pstate & DBG_SPSR_SS) { > + mdscr = read_sysreg(mdscr_el1); > + write_sysreg(mdscr & ~DBG_MDSCR_SS, mdscr_el1); > + } I think this will break the implicit handling of kernel {break,watch}points. Sadly, I think any attempts to workaround the issues here are likely just to push the problems around. We really need to overhaul the debug exception handling logic we have, which means I need to get back to writing up a proposal. Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel