Re: [PATCH v12 00/18] drm: Add Samsung MIPI DSIM bridge

Alexander Stein
2023-02-17T10:06:33Z

Am Freitag, 17. Februar 2023, 09:55:22 CET schrieb Rasmus Villemoes:
> On 14/02/2023 12.09, Fabio Estevam wrote:
> > Hi Rasmus,
> >
> > On Tue, Feb 14, 2023 at 7:55 AM Rasmus Villemoes
> >
> > <rasmus.villemoes@prevas.dk> wrote:
> >> Well, the data sheet for the dsi86 says up to 750MHz DSI HS clock, and
> >> if the value specified in samsung,burst-clock-frequency is twice the DSI
> >> HS clk, I suppose I should be good up to 1.5GHz? I have tried many
> >> different values, but I never seem to get anything through; I think I'm
> >> missing some piece.
> >>
> >> So now I've tried to use these patches on the imx8mp-evk with the
> >> mipi->hdmi accessory from NXP, just to see if I can ever get any
> >> graphics through the mipi interface. And there the story is the same:
> >> the adv7535 bridge gets probed, and can read out the edid from the
> >> monitor over hdmi. And while the mipi block and the bridge seem to
> >> attach to each other, I still don't get any output.
> >>
> >> Do any of you happen to have this working on the imx8mp-evk, and if so,
> >> can you share the .dts updates you've done and how exactly you test the
> >> graphics?
> >
> > I don't have access to an imx8mp-evk, but I tested the ADV7535 MIPI to
> > HDMI daughter card on an imx8mm-evk.
> >
> > Some extra ADV7535 patches were needed. Please check patches 0020-0023
> > and see if they help.
>
> Thanks, but they don't seem to make a difference.
>
> I've started trying to simply compare registers between the NXP 5.15
> kernel and the imx8mm-dsi-v12 branch with Marek's patch on top. Already
> in MEDIA_BLK_CTRL, 0x32ec0000, there's something interesting:
>
> ## Media Mix Clock Enable Register
> -CLK_EN 0004 0080e133
> +CLK_EN 0004 00800133
> ## MIPI PHY Control Register
> -MIPI_RESET_DIV 0008 40030000
> +MIPI_RESET_DIV 0008 00020000
>
> So with the NXP kernel, there are three bits set in CLK_EN which are not
> set with the "mainline", but those bits are marked reserved in the RM,
> so I have no idea if they are just some RO bits that get set due to some
> other munging. Then there's the MIPI_RESET_DIV register where bits 16
> and 30 do not get set. Of course, there are lots of other differences,
> but perhaps this gives somebody an idea.

Looking at drivers/soc/imx/imx8m-blk-ctrl.c the bits for MIPI_RESET_DIV are
16: MIPI_CSI1
17: MIPI_DSI
30: MIPI_CSI2
So i think that's okay here.

Best regards,
Alexander
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