Re: [PATCH] ARM: dts: allwinner: minimize irq debounce filter per default

[Maxime Ripard <maxime@cerno.tech>]

[-- Attachment #1.1: Type: text/plain, Size: 3668 bytes --]

On Fri, Feb 10, 2023 at 09:44:25AM +0000, Andre Przywara wrote:
> On Fri, 10 Feb 2023 09:29:36 +0100
> Maxime Ripard <maxime@cerno.tech> wrote:
> 
> Hi Maxime,
> 
> thanks for the reply!
> 
> > On Thu, Feb 09, 2023 at 08:29:52PM +0000, Andre Przywara wrote:
> > > > >>   &pio {
> > > > >> +	/* 1�s debounce filter on both IRQ banks */  
> > > > > Is that supposed to be <micro> in UTF-8? It seems to have got lost in
> > > > > translation, or is that just me?  
> > > > O yes, the Greek character slipped into the comment.  
> > > > >> +	input-debounce = <1 1>;  
> > > > > As mentioned above, I am not so sure this is generic enough to put it
> > > > > here for PA. And what is the significance of "1 us", in particular? Is
> > > > > that just the smallest value?    
> > > > 
> > > > Yes indeed it's a bit more complicated than I feel it needs to be. The
> > > > configuration is taken as microseconds and translated into the best
> > > > matching clock and divider by the driver. However, 0 is not translated
> > > > to the lowest divider of the high speed clock as would be logical if
> > > > you ask for zero microseconds, but to "leave at default". The default
> > > > of the board is 0 in the register, translating to lowest divider on the
> > > > _low_ speed clock.  
> > > 
> > > I'd say the "if (!debounce) continue;" code is just to defend against
> > > the division by zero, which would be the next statement to execute.
> > > 
> > > We might want to change that to interpret 0 as "lowest possible", which
> > > would be 24MHz/1. Please feel free to send a patch in this regard, and
> > > CC: Maxime, to get some input on that idea.  
> > 
> > I never had any complaint on that part either, so the default looks sane
> > to me.
> > 
> > If some board needs a higher debouncing rate, then we should obviously
> > set it up in the device tree of that board, but changing it for every
> > user also introduces the risk of breaking other boards that actually
> > require a lower debouncing frequency.
> 
> Yeah, we definitely should keep the default at 32KHz/1, as this is also
> the hardware reset value.
> 
> Not sure if you were actually arguing this, but the change I sketched
> above (interpreting 0 as 24MHz/1) is separate though, as the current
> default is "no DT property", and not 0. There is no input-debounce
> property user in the kernel tree at the moment, so we wouldn't break
> anyone. The only thing that would change is if a downstream user was
> relying on "0" being interpreted as "skip the setup", which isn't
> really documented and could be argued to be an implementation detail.
> 
> So I'd suggest to implement 0 as "lowest possible", and documenting that
> and the 32KHz/1 default if no property is given.

Ah, my bad.

There's another thing to consider: there's already a generic per-pin
input-debounce property in pinctrl.

Since we can't control it per pin but per bank, we moved it to the
controller back then, but there's always been this (implicit)
expectation that it was behaving the same way.

And the generic, per-pin, input-debounce documentation says:

> Takes the debounce time in usec as argument or 0 to disable debouncing

I agree that silently ignoring it is not great, but interpreting 0 as
the lowest possible is breaking that behaviour which, I believe, is a
worse outcome.

So I'm not sure what's the best course of action here. Rejecting the
configuration entirely would prevent the entire pinctrl driver from
probing which sounds really bad. Maybe we could just print an error that
we rejected it to make it more obvious?

Maxime

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[-- Attachment #2: Type: text/plain, Size: 176 bytes --]

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel