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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id v14-20020a9d604e000000b006864816ecd9sm2849948otj.59.2023.02.27.10.55.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 10:55:58 -0800 (PST) Received: (nullmailer pid 675791 invoked by uid 1000); Mon, 27 Feb 2023 18:55:57 -0000 Date: Mon, 27 Feb 2023 12:55:57 -0600 From: Rob Herring To: Elad Nachman Cc: thomas.petazzoni@bootlin.com, bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 4/7] dt-bindings: PCI: dwc: add DMA, region mask bits Message-ID: <20230227185557.GA672128-robh@kernel.org> References: <20230223180531.15148-1-enachman@marvell.com> <20230223180531.15148-5-enachman@marvell.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230223180531.15148-5-enachman@marvell.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230227_105600_679856_8B434BB9 X-CRM114-Status: GOOD ( 19.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Feb 23, 2023 at 08:05:28PM +0200, Elad Nachman wrote: > From: Elad Nachman > > Add properties to support configurable DMA mask bits > and region mask bits. > configurable DMA mask bits is needed for Marvell AC5/AC5X SOCs which > have their physical DDR memory start at address 0x2_0000_0000. > Configurable region mask bits is needed for the Marvell Armada > 7020/7040/8040 SOCs when the DT file places the PCIe window above the > 4GB region. > The Synopsis Designware PCIe IP in these SOCs is too old to specify the > highest memory location supported by the PCIe, but practically supports > such locations. Allow these locations to be specified in the DT file. > First DT property is called num-dmamask, > and can range between 33 and 64. > Second DT property is called num-regionmask, > and can range between 33 and 64. > > Signed-off-by: Elad Nachman > --- > .../devicetree/bindings/pci/snps,dw-pcie-common.yaml | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml > index d87e13496834..a1b06ff19ca7 100644 > --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml > +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml > @@ -261,6 +261,16 @@ properties: > > dma-coherent: true > > + num-dmamask: Nope! There's already a defined way to define DMA/bus addresses and sizes in DT. That's dma-ranges. Rob _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel