From: Siddharth Vadapalli <s-vadapalli@ti.com>
To: <vkoul@kernel.org>, <kishon@kernel.org>, <rogerq@kernel.org>
Cc: <linux-phy@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <srk@ti.com>,
<s-vadapalli@ti.com>
Subject: [PATCH v2 2/3] phy: ti: gmii-sel: Enable SGMII mode for J7200
Date: Thu, 9 Mar 2023 12:05:13 +0530 [thread overview]
Message-ID: <20230309063514.398705-3-s-vadapalli@ti.com> (raw)
In-Reply-To: <20230309063514.398705-1-s-vadapalli@ti.com>
TI's J7200 SoC supports SGMII mode with the CPSW5G instance of the CPSW
Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the
corresponding extra_modes member.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
drivers/phy/ti/phy-gmii-sel.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
index 5e16d8dd5bee..f3da6b020247 100644
--- a/drivers/phy/ti/phy-gmii-sel.c
+++ b/drivers/phy/ti/phy-gmii-sel.c
@@ -221,7 +221,7 @@ static const
struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j7200 = {
.use_of_data = true,
.regfields = phy_gmii_sel_fields_am654,
- .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII),
+ .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
.num_ports = 4,
.num_qsgmii_main_ports = 1,
};
--
2.25.1
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next prev parent reply other threads:[~2023-03-09 6:36 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-09 6:35 [PATCH v2 0/3] PHY-GMII-SEL: Add support for SGMII mode Siddharth Vadapalli
2023-03-09 6:35 ` [PATCH v2 1/3] phy: ti: gmii-sel: " Siddharth Vadapalli
2023-03-09 6:35 ` Siddharth Vadapalli [this message]
2023-03-09 6:35 ` [PATCH v2 3/3] phy: ti: gmii-sel: Enable SGMII mode for J721E Siddharth Vadapalli
2023-04-04 7:04 ` [PATCH v2 0/3] PHY-GMII-SEL: Add support for SGMII mode Siddharth Vadapalli
2023-04-04 12:13 ` Roger Quadros
2023-05-16 14:31 ` Vinod Koul
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