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[5.69.146.176]) by smtp.gmail.com with ESMTPSA id t15-20020adfe10f000000b002c5526234d2sm2089144wrz.8.2023.03.10.04.54.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Mar 2023 04:54:51 -0800 (PST) Date: Fri, 10 Mar 2023 12:54:53 +0000 From: Jean-Philippe Brucker To: Nicolin Chen Cc: Jason Gunthorpe , robin.murphy@arm.com, will@kernel.org, eric.auger@redhat.com, kevin.tian@intel.com, baolu.lu@linux.intel.com, joro@8bytes.org, shameerali.kolothum.thodi@huawei.com, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, yi.l.liu@intel.com Subject: Re: [PATCH v1 02/14] iommufd: Add nesting related data structures for ARM SMMUv3 Message-ID: <20230310125453.GB1745536@myrica> References: <364cfbe5b228ab178093db2de13fa3accf7a6120.1678348754.git.nicolinc@nvidia.com> <20230309134217.GA1673607@myrica> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230310_045456_627621_E6FE30FE X-CRM114-Status: GOOD ( 16.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Mar 09, 2023 at 08:50:52PM -0800, Nicolin Chen wrote: > On Thu, Mar 09, 2023 at 10:48:50AM -0400, Jason Gunthorpe wrote: > > > Nicolin, I think we should tweak the uAPI here so that the > > invalidation opaque data has a format tagged on its own, instead of > > re-using the HWPT tag. Ie you can have a ARM SMMUv3 invalidate type > > tag and also a virtio-viommu invalidate type tag. > > The invalidation tage is shared with the hwpt allocation. Does > it mean that virtio-iommu won't have it's own allocation tag? I'm not entirely sure what you mean by allocation tag. For example with SMMU, when attaching page tables (SMMUv2), the guest passes an ASID at allocation, and when it modifies that address space it passes the same ASID for invalidation. When attaching PASID tables (SMMUv3), it writes the ASID/PASID in the PASID table, and passes both in the invalidation. Note that none of this is set in stone. It copies the Linux API we originally discussed, but we were waiting for progress on that front before committing to anything. Now we'll probably align to the new API where possible, leaving out what doesn't work for virtio-iommu. Thanks, Jean _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel