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From: Chester Lin <clin@suse.com>
To: Linus Walleij <linus.walleij@linaro.org>,
	Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: "Chester Lin" <clin@suse.com>, "NXP S32 Linux Team" <s32@nxp.com>,
	linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	"Ghennadi Procopciuc" <Ghennadi.Procopciuc@oss.nxp.com>,
	"Andrei Stefanescu" <andrei.stefanescu@nxp.com>,
	"Radu Pirea" <radu-nicolae.pirea@nxp.com>,
	"Andreas Färber" <afaerber@suse.de>,
	"Matthias Brugger" <mbrugger@suse.com>
Subject: [PATCH 2/3] pinctrl: s32cc: refactor pin config parsing
Date: Tue, 14 Mar 2023 21:46:41 +0800	[thread overview]
Message-ID: <20230314134642.21535-3-clin@suse.com> (raw)
In-Reply-To: <20230314134642.21535-1-clin@suse.com>

Move common codes into smaller inline functions and remove some argument
handlings that are not actually used by either S32 MSCR register or generic
config params.

Signed-off-by: Chester Lin <clin@suse.com>
---
 drivers/pinctrl/nxp/pinctrl-s32cc.c | 82 ++++++++++++++++++-----------
 1 file changed, 50 insertions(+), 32 deletions(-)

diff --git a/drivers/pinctrl/nxp/pinctrl-s32cc.c b/drivers/pinctrl/nxp/pinctrl-s32cc.c
index 7a38e3216b0c..9508fc1e9a90 100644
--- a/drivers/pinctrl/nxp/pinctrl-s32cc.c
+++ b/drivers/pinctrl/nxp/pinctrl-s32cc.c
@@ -39,6 +39,9 @@
 #define S32_MSCR_ODE		BIT(20)
 #define S32_MSCR_OBE		BIT(21)
 
+#define S32_CFG_SET		true
+#define S32_CFG_CLR		false
+
 static struct regmap_config s32_regmap_config = {
 	.reg_bits = 32,
 	.val_bits = 32,
@@ -475,32 +478,57 @@ static int s32_get_slew_regval(int arg)
 	return -EINVAL;
 }
 
-static int s32_get_pin_conf(enum pin_config_param param, u32 arg,
-			    unsigned int *mask, unsigned int *config)
+static inline void s32_pin_config(unsigned int *mask, unsigned int *config,
+				  unsigned int bits, bool set)
+{
+	if (set)
+		*config |= bits;
+	else
+		*config &= ~bits;
+	*mask |= bits;
+}
+
+static inline void s32_pull_enable(enum pin_config_param param,
+				   unsigned int *mask, unsigned int *config)
+{
+
+	if (param == PIN_CONFIG_BIAS_PULL_UP) {
+		s32_pin_config(mask, config, S32_MSCR_PUS | S32_MSCR_PUE,
+			       S32_CFG_SET);
+	} else if (param == PIN_CONFIG_BIAS_PULL_DOWN) {
+		*config &= ~S32_MSCR_PUS;
+		*config |= S32_MSCR_PUE;
+		*mask |= S32_MSCR_PUS | S32_MSCR_PUE;
+	}
+}
+
+static inline void s32_pull_disable(unsigned int *mask, unsigned int *config)
+{
+	s32_pin_config(mask, config, S32_MSCR_PUS | S32_MSCR_PUE, S32_CFG_CLR);
+}
+
+static int s32_parse_pincfg(unsigned long pincfg, unsigned int *mask,
+			    unsigned int *config)
 {
+	enum pin_config_param param;
+	u32 arg;
 	int ret;
 
+	param = pinconf_to_config_param(pincfg);
+	arg = pinconf_to_config_argument(pincfg);
+
 	switch (param) {
 	/* All pins are persistent over suspend */
 	case PIN_CONFIG_PERSIST_STATE:
 		return 0;
 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
-		*config |= S32_MSCR_ODE;
-		*mask |= S32_MSCR_ODE;
+		s32_pin_config(mask, config, S32_MSCR_ODE, S32_CFG_SET);
 		break;
 	case PIN_CONFIG_OUTPUT_ENABLE:
-		if (arg)
-			*config |= S32_MSCR_OBE;
-		else
-			*config &= ~S32_MSCR_OBE;
-		*mask |= S32_MSCR_OBE;
+		s32_pin_config(mask, config, S32_MSCR_OBE, S32_CFG_SET);
 		break;
 	case PIN_CONFIG_INPUT_ENABLE:
-		if (arg)
-			*config |= S32_MSCR_IBE;
-		else
-			*config &= ~S32_MSCR_IBE;
-		*mask |= S32_MSCR_IBE;
+		s32_pin_config(mask, config, S32_MSCR_IBE, S32_CFG_SET);
 		break;
 	case PIN_CONFIG_SLEW_RATE:
 		ret = s32_get_slew_regval(arg);
@@ -510,25 +538,17 @@ static int s32_get_pin_conf(enum pin_config_param param, u32 arg,
 		*mask |= S32_MSCR_SRE(~0);
 		break;
 	case PIN_CONFIG_BIAS_PULL_UP:
-		if (arg)
-			*config |= S32_MSCR_PUS;
-		else
-			*config &= ~S32_MSCR_PUS;
-		fallthrough;
 	case PIN_CONFIG_BIAS_PULL_DOWN:
-		if (arg)
-			*config |= S32_MSCR_PUE;
-		else
-			*config &= ~S32_MSCR_PUE;
-		*mask |= S32_MSCR_PUE | S32_MSCR_PUS;
+		s32_pull_enable(param, mask, config);
 		break;
 	case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
-		*config &= ~(S32_MSCR_ODE | S32_MSCR_OBE | S32_MSCR_IBE);
-		*mask |= S32_MSCR_ODE | S32_MSCR_OBE | S32_MSCR_IBE;
-		fallthrough;
+		s32_pin_config(mask, config,
+			       S32_MSCR_ODE | S32_MSCR_OBE | S32_MSCR_IBE,
+			       S32_CFG_CLR);
+		s32_pull_disable(mask, config);
+		break;
 	case PIN_CONFIG_BIAS_DISABLE:
-		*config &= ~(S32_MSCR_PUS | S32_MSCR_PUE);
-		*mask |= S32_MSCR_PUS | S32_MSCR_PUE;
+		s32_pull_disable(mask, config);
 		break;
 	default:
 		return -EOPNOTSUPP;
@@ -554,9 +574,7 @@ static int s32_pinconf_mscr_update(struct pinctrl_dev *pctldev,
 		pin_get_name(pctldev, pin_id), num_configs);
 
 	for (i = 0; i < num_configs; i++) {
-		ret = s32_get_pin_conf(pinconf_to_config_param(configs[i]),
-				       pinconf_to_config_argument(configs[i]),
-				       &mask, &config);
+		ret = s32_parse_pincfg(configs[i], &mask, &config);
 		if (ret)
 			return ret;
 	}
-- 
2.37.3


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  parent reply	other threads:[~2023-03-14 13:48 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-14 13:46 [PATCH 0/3] pinctrl: s32: driver improvements and generic struct use Chester Lin
2023-03-14 13:46 ` [PATCH 1/3] pinctrl: s32: refine error/return/config checks and simplify driver codes Chester Lin
2023-03-14 17:08   ` Andy Shevchenko
2023-03-14 13:46 ` Chester Lin [this message]
2023-03-14 17:15   ` [PATCH 2/3] pinctrl: s32cc: refactor pin config parsing Andy Shevchenko
2023-03-14 13:46 ` [PATCH 3/3] pinctrl: s32cc: embed generic struct pingroup and pinfunction Chester Lin
2023-03-14 17:19   ` Andy Shevchenko
2023-03-14 17:21 ` [PATCH 0/3] pinctrl: s32: driver improvements and generic struct use Andy Shevchenko
2023-03-17  3:45   ` Chester Lin

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