From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 63470C6FD1D for ; Mon, 20 Mar 2023 10:48:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=UToYWj3OoDcNUFJ8lJog26GRNlA/FpoMbfXuXWLpCHQ=; b=JW58Em3SJiWuuC b9pKvJxHupuQi1DDTPxuYWS577S1/q1aIUnWTJlSyOWOaRhZCbrtAudqQsIpP7Rav11DaBVCsudm6 p8nh8BVcTEFhaj1StDJ5yvLtfHgyCJz8Y5NIJtGPqYNJiypIgaUQLUNAi2N+gaROS2NE+9bZ+N+33 dUdmiFdhDQCmoQ86vWonDLGYv45smmaSvs49ool+ECdAdORLtiyB71ISNn6IT0FBPnX3POqc3H1SY +3zJD0AXaHjQpY7X2gb6pKDOj/xaDB1FtrQJ/1aZlXsdTlUyOn6uZ6X8N5y4CCmhIyGT/g+CY3bH+ dMjWEAC9JMiEG+WrfyRA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1peD3c-008hNB-2d; Mon, 20 Mar 2023 10:48:04 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1peD3Z-008hMR-25 for linux-arm-kernel@lists.infradead.org; Mon, 20 Mar 2023 10:48:03 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9D103FEC; Mon, 20 Mar 2023 03:48:39 -0700 (PDT) Received: from bogus (unknown [10.57.52.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C4B463F67D; Mon, 20 Mar 2023 03:47:52 -0700 (PDT) Date: Mon, 20 Mar 2023 10:47:19 +0000 From: Sudeep Holla To: Shanker Donthineni Cc: Marc Zyngier , Catalin Marinas , Sudeep Holla , Will Deacon , Jonathan Corbet , Mark Rutland , Lorenzo Pieralisi , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Vikram Sethi , Thierry Reding Subject: Re: [PATCH v5] irqchip/gicv3: Workaround for NVIDIA erratum T241-FABRIC-4 Message-ID: <20230320104719.mane5faxvv6ofpiv@bogus> References: <20230319024314.3540573-1-sdonthineni@nvidia.com> <20230319024314.3540573-2-sdonthineni@nvidia.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230319024314.3540573-2-sdonthineni@nvidia.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230320_034801_806734_1B69C39E X-CRM114-Status: GOOD ( 21.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, Mar 18, 2023 at 09:43:14PM -0500, Shanker Donthineni wrote: > The T241 platform suffers from the T241-FABRIC-4 erratum which causes > unexpected behavior in the GIC when multiple transactions are received > simultaneously from different sources. This hardware issue impacts > NVIDIA server platforms that use more than two T241 chips > interconnected. Each chip has support for 320 {E}SPIs. > > This issue occurs when multiple packets from different GICs are > incorrectly interleaved at the target chip. The erratum text below > specifies exactly what can cause multiple transfer packets susceptible > to interleaving and GIC state corruption. GIC state corruption can > lead to a range of problems, including kernel panics, and unexpected > behavior. > > From the erratum text: > "In some cases, inter-socket AXI4 Stream packets with multiple > transfers, may be interleaved by the fabric when presented to ARM > Generic Interrupt Controller. GIC expects all transfers of a packet > to be delivered without any interleaving. > > The following GICv3 commands may result in multiple transfer packets > over inter-socket AXI4 Stream interface: > - Register reads from GICD_I* and GICD_N* > - Register writes to 64-bit GICD registers other than GICD_IROUTERn* > - ITS command MOVALL > > Multiple commands in GICv4+ utilize multiple transfer packets, > including VMOVP, VMOVI, VMAPP, and 64-bit register accesses." > > This issue impacts system configurations with more than 2 sockets, > that require multi-transfer packets to be sent over inter-socket > AXI4 Stream interface between GIC instances on different sockets. > GICv4 cannot be supported. GICv3 SW model can only be supported > with the workaround. Single and Dual socket configurations are not > impacted by this issue and support GICv3 and GICv4." > > Link: https://developer.nvidia.com/docs/t241-fabric-4/nvidia-t241-fabric-4-errata.pdf > > Writing to the chip alias region of the GICD_In{E} registers except > GICD_ICENABLERn has an equivalent effect as writing to the global > distributor. The SPI interrupt deactivate path is not impacted by > the erratum. > > To fix this problem, implement a workaround that ensures read accesses > to the GICD_In{E} registers are directed to the chip that owns the > SPI, and disable GICv4.x features. To simplify code changes, the > gic_configure_irq() function uses the same alias region for both read > and write operations to GICD_ICFGR. > > Co-developed-by: Vikram Sethi > Signed-off-by: Vikram Sethi > Signed-off-by: Shanker Donthineni > --- > Changes since v4: > - Resolve Marc's comments https://lore.kernel.org/all/871qlqif9v.wl-maz@kernel.org/ > Changes since v3: > - Fix the build issue for the 32bit arch > Changes since v2: > - Add accessors for the SOC-ID version & revision SMCCC/SOC ID part looks good to me. In case you spin another version for any reason, I would prefer you split those changes into separate patch. Otherwise Acked-by: Sudeep Holla (for SMCCC/SOC ID bits) -- Regards, Sudeep _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel