From: Rob Herring <robh@kernel.org>
To: Jian Yang <jian.yang@mediatek.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lpieralisi@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Jianjun Wang <jianjun.wang@mediatek.com>,
linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Project_Global_Chrome_Upstream_Group@mediatek.com,
chuanjia.liu@mediatek.com, jieyy.yang@mediatek.com,
qizhong.cheng@mediatek.com
Subject: Re: [PATCH v2 2/2] PCI: mediatek-gen3: Add power and reset control feature for downstream component
Date: Tue, 21 Mar 2023 11:57:55 -0500 [thread overview]
Message-ID: <20230321165755.GA942823-robh@kernel.org> (raw)
In-Reply-To: <20230306064059.7239-3-jian.yang@mediatek.com>
On Mon, Mar 06, 2023 at 02:40:59PM +0800, Jian Yang wrote:
> From: "jian.yang" <jian.yang@mediatek.com>
>
> Make MediaTek's controller driver capable of controlling power
> supplies and reset pin of a downstream component in power-on and
> power-off flow.
>
> Some downstream components (e.g., a WIFI chip) may need an extra
> reset other than PERST# and their power supplies, depending on
> the requirements of platform, may need to controlled by their
> parent's driver. To meet the requirements described above, I add this
> feature to MediaTek's PCIe controller driver as a optional feature.
If you have PCI devices with extra stuff that's not standard PCI stuff
(i.e. what's on a standard connector), then you should be describing
the PCI device in the DT.
The standard stuff should really be in the root port node rather than
the host bridge node. That's often omitted too because many host bridges
only have a single root port.
>
> Signed-off-by: jian.yang <jian.yang@mediatek.com>
> ---
> drivers/pci/controller/pcie-mediatek-gen3.c | 86 ++++++++++++++++++++-
> 1 file changed, 85 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
> index b8612ce5f4d0..45e368b03ed2 100644
> --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> @@ -8,6 +8,8 @@
>
> #include <linux/clk.h>
> #include <linux/delay.h>
> +#include <linux/gpio.h>
> +#include <linux/gpio/consumer.h>
> #include <linux/iopoll.h>
> #include <linux/irq.h>
> #include <linux/irqchip/chained_irq.h>
> @@ -15,11 +17,14 @@
> #include <linux/kernel.h>
> #include <linux/module.h>
> #include <linux/msi.h>
> +#include <linux/of_gpio.h>
This header is getting removed. You shouldn't depend on it.
Rob
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next prev parent reply other threads:[~2023-03-21 16:59 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-06 6:40 [PATCH v2 0/2] PCI: mediatek-gen3: Support controlling power and Jian Yang
2023-03-06 6:40 ` [PATCH v2 1/2] dt-bindings: PCI: mediatek-gen3: Add support for controlling power and reset Jian Yang
2023-03-06 6:40 ` [PATCH v2 2/2] PCI: mediatek-gen3: Add power and reset control feature for downstream component Jian Yang
2023-03-21 16:57 ` Rob Herring [this message]
2023-04-04 2:43 ` Jian Yang (杨戬)
2023-03-20 9:02 ` [PATCH v2 0/2] PCI: mediatek-gen3: Support controlling power and Jian Yang (杨戬)
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