From: Conor Dooley <conor@kernel.org>
To: Pierre Gondois <pierre.gondois@arm.com>
Cc: linux-kernel@vger.kernel.org, Radu Rendec <rrendec@redhat.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Sudeep Holla <sudeep.holla@arm.com>,
Akihiko Odaki <akihiko.odaki@daynix.com>,
Palmer Dabbelt <palmer@rivosinc.com>,
Gavin Shan <gshan@redhat.com>,
Jeremy Linton <jeremy.linton@arm.com>,
linux-arm-kernel@lists.infradead.org,
Alexandre Ghiti <alex@ghiti.fr>
Subject: Re: [PATCH 2/3] cacheinfo: Check cache properties are present in DT
Date: Tue, 4 Apr 2023 20:29:46 +0100 [thread overview]
Message-ID: <20230404-hatred-swimmer-6fecdf33b57a@spud> (raw)
In-Reply-To: <20230327115953.788244-3-pierre.gondois@arm.com>
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Hey Pierre,
On Mon, Mar 27, 2023 at 01:59:50PM +0200, Pierre Gondois wrote:
> If a Device Tree (DT) is used, the presence of cache properties is
> assumed. Not finding any is not considered. For arm64 platforms,
> cache information can be fetched from the clidr_el1 register.
> Checking whether cache information is available in the DT
> allows to switch to using clidr_el1.
>
> init_of_cache_level()
> \-of_count_cache_leaves()
> will assume there a 2 cache leaves (L1 data/instruction caches), which
> can be different from clidr_el1 information.
>
> cache_setup_of_node() tries to read cache properties in the DT.
> If there are none, this is considered a success. Knowing no
> information was available would allow to switch to using clidr_el1.
>
Alex reported seeing a bunch of messages in his boot log in QEMU since
-rc1 which appears to be the fault of, as far as I can tell, e0df442ee49
("cacheinfo: Check 'cache-unified' property to count cache leaves")
like:
cacheinfo: Unable to detect cache hierarchy for CPU N
The RISC-V QEMU virt machine doesn't define any cache properties of any
sort in the dtb, and unlike the arm64 virt machine I tried (a72) doesn't
have some registers that cache info is discoverable from.
When we call of_count_cache_leaves() from init_of_cache_level() and
there are of course no reasons to increment leaves, we hit the return 2
case you mention above, setting num_leaves to 2.
As you mention, when we hit cache_setup_of_node(), levels is not going
to be set to one, so we trigger the condition (this_leaf->level != 1)
and, as there are no cache nodes, break out of the loop without
incrementing index. Index is therefore less than 2, and thus we return
-ENOENT.
This is of course propagated back out to detect_cache_attributes() and
triggers the "Unable to detect..." printout :(
With this patch(set), the spurious error prints go away, but we are left
with a "Early cacheinfo failed, ret = -22" which will need to be fixed.
So I think this also needs to be:
Fixes: de0df442ee49 ("cacheinfo: Check 'cache-unified' property to count cache leaves")
Probably also needs a:
Reported-by: Alexandre Ghiti <alexghiti@rivosinc.com>
since he's found an actual, rather than theoretical, problem!
Cheers,
Conor.
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
> ---
> drivers/base/cacheinfo.c | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
> index 4ca117574af1..5b0edf2d5da8 100644
> --- a/drivers/base/cacheinfo.c
> +++ b/drivers/base/cacheinfo.c
> @@ -78,6 +78,9 @@ bool last_level_cache_is_shared(unsigned int cpu_x, unsigned int cpu_y)
> }
>
> #ifdef CONFIG_OF
> +
> +static bool of_check_cache_nodes(struct device_node *np);
> +
> /* OF properties to query for a given cache type */
> struct cache_type_info {
> const char *size_prop;
> @@ -205,6 +208,11 @@ static int cache_setup_of_node(unsigned int cpu)
> return -ENOENT;
> }
>
> + if (!of_check_cache_nodes(np)) {
> + of_node_put(np);
> + return -ENOENT;
> + }
> +
> prev = np;
>
> while (index < cache_leaves(cpu)) {
> @@ -229,6 +237,25 @@ static int cache_setup_of_node(unsigned int cpu)
> return 0;
> }
>
> +static bool of_check_cache_nodes(struct device_node *np)
> +{
> + struct device_node *next;
> +
> + if (of_property_read_bool(np, "cache-size") ||
> + of_property_read_bool(np, "i-cache-size") ||
> + of_property_read_bool(np, "d-cache-size") ||
> + of_property_read_bool(np, "cache-unified"))
> + return true;
> +
> + next = of_find_next_cache_node(np);
> + if (next) {
> + of_node_put(next);
> + return true;
> + }
> +
> + return false;
> +}
> +
> static int of_count_cache_leaves(struct device_node *np)
> {
> unsigned int leaves = 0;
> @@ -260,6 +287,9 @@ int init_of_cache_level(unsigned int cpu)
> struct device_node *prev = NULL;
> unsigned int levels = 0, leaves, level;
>
> + if (!of_check_cache_nodes(np))
> + goto err_out;
> +
> leaves = of_count_cache_leaves(np);
> if (leaves > 0)
> levels = 1;
> --
> 2.25.1
>
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next prev parent reply other threads:[~2023-04-04 19:30 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-27 11:59 [PATCH 0/3] cacheinfo: Correctly fallback to using clidr_el1's information Pierre Gondois
2023-03-27 11:59 ` [PATCH 1/3] cacheinfo: Check sib_leaf in cache_leaves_are_shared() Pierre Gondois
2023-03-27 14:04 ` Conor Dooley
2023-03-27 11:59 ` [PATCH 2/3] cacheinfo: Check cache properties are present in DT Pierre Gondois
2023-03-27 14:13 ` Conor Dooley
2023-04-04 19:29 ` Conor Dooley [this message]
2023-04-06 7:31 ` Pierre Gondois
2023-03-27 11:59 ` [PATCH 3/3] cacheinfo: Add use_arch[|_cache]_info field/function Pierre Gondois
2023-03-27 12:17 ` Will Deacon
2023-04-06 7:28 ` Pierre Gondois
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