From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5747EC7619A for ; Tue, 11 Apr 2023 11:26:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=iWeMxgwA5Qrbtbqyf4eGnSEjfu4j1RJJDPSK+3mpoFo=; b=t/AmSkjYu+pVXA Ui9pPbIBNlWnSWrwuQ+G4MDtJgp3oPgu4bgVpGcHGHZsFoHYQwj76IXPKwaNfpHjQPdcZ1alREdo4 c7cqiq3V+E4G06HD/hualGhD/wcD2su9uPALvKIIB1X3/YSFs66tArmoZChTcYgncJ1130wgkqkw2 hdj+SEreOk55uTBRl/CHqz8B8L0WESR/DcpbkKwT+DWmGdXHqC1pt0/rtUvHsmPOy4lRZvNtF4R2R xr+r13mqNAX0ptI+b93v+TxlIimYA7iiVT0D8uiP2ixNOc49g0wXX16OOKCIsQpQrj2CdUBtSp88m FUHSxF0zrvE8OGfLy/qQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pmC7c-00HRLk-18; Tue, 11 Apr 2023 11:25:12 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pmC7Y-00HRKq-21 for linux-arm-kernel@lists.infradead.org; Tue, 11 Apr 2023 11:25:11 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E9F4D61D84; Tue, 11 Apr 2023 11:25:06 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2CB2BC433EF; Tue, 11 Apr 2023 11:25:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1681212306; bh=B1ZaBaMT7tK1LgbIC9hi0qnUcpYo7fHssf6FQgCYUSc=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=b+6K2xiSZW9LeODlX6QGkuBhaatbr6qJ04rVPuUT9yhUF9ts+pT4CHfnTiJ3DfGFb eTlekH9JjtnX8/ZH8bYitLFueHoRKQJomQHbalxo1LpxMQEZlR3DiBIoi4nVPLFnf9 hbwl+YJHksmSTQKbYBkWj7OY1g5marypXanq7RQe1t9PEjg43vhMNm8Xao9pq1ZVHw qhq/oz5ckYg3iGq4p+W1mBvqy20+olh6dtQFvvMgrrVoTkAVpCgrTol0L2tqL3CQ0U iLB8lYWxk9uWObv+f8uFxAL+ZXJyUklNvfpYKjxeBzvWmcfIkKyb2rfn3Dg6+V8OYo 1OMuU0QwnFKHA== Date: Tue, 11 Apr 2023 12:24:59 +0100 From: Will Deacon To: Marc Zyngier Cc: Reiji Watanabe , Mark Rutland , Oliver Upton , Catalin Marinas , kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Zenghui Yu , Suzuki K Poulose , Paolo Bonzini , Ricardo Koller , Jing Zhang , Raghavendra Rao Anata , Shaoqin Huang , Rob Herring Subject: Re: [PATCH v2 0/2] KVM: arm64: PMU: Correct the handling of PMUSERENR_EL0 Message-ID: <20230411112458.GA22090@willie-the-truck> References: <20230408034759.2369068-1-reijiw@google.com> <86r0subv8s.wl-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <86r0subv8s.wl-maz@kernel.org> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230411_042508_763064_210BDFC3 X-CRM114-Status: GOOD ( 29.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, Apr 08, 2023 at 10:04:19AM +0100, Marc Zyngier wrote: > On Sat, 08 Apr 2023 04:47:57 +0100, > Reiji Watanabe wrote: > > > > This series will fix bugs in KVM's handling of PMUSERENR_EL0. > > > > With PMU access support from EL0 [1], the perf subsystem would > > set CR and ER bits of PMUSERENR_EL0 as needed to allow EL0 to have > > a direct access to PMU counters. However, KVM appears to assume > > that the register value is always zero for the host EL0, and has > > the following two problems in handling the register. > > > > [A] The host EL0 might lose the direct access to PMU counters, as > > KVM always clears PMUSERENR_EL0 before returning to userspace. > > > > [B] With VHE, the guest EL0 access to PMU counters might be trapped > > to EL1 instead of to EL2 (even when PMUSERENR_EL0 for the guest > > indicates that the guest EL0 has an access to the counters). > > This is because, with VHE, KVM sets ER, CR, SW and EN bits of > > PMUSERENR_EL0 to 1 on vcpu_load() to ensure to trap PMU access > > from the guset EL0 to EL2, but those bits might be cleared by > > the perf subsystem after vcpu_load() (when PMU counters are > > programmed for the vPMU emulation). > > > > Patch-1 will fix [A], and Patch-2 will fix [B] respectively. > > The series is based on v6.3-rc5. > > > > v2: > > - Save the PMUSERENR_EL0 for the host in the sysreg array of > > kvm_host_data. [Marc] > > - Don't let armv8pmu_start() overwrite PMUSERENR if the vCPU > > is loaded, instead have KVM update the saved shadow register > > value for the host. [Marc, Mark] > > This looks much better to me. If Mark is OK with it, I'm happy to take > it in 6.4. > > Speaking of which, this will clash with the queued move of the PMUv3 > code into drivers/perf, and probably break on 32bit. I can either take > a branch shared with arm64 (009d6dc87a56 ("ARM: perf: Allow the use of > the PMUv3 driver on 32bit ARM")), or wait until -rc1. > > Will, what do you prefer? I'd be inclined to wait until -rc1, but for-next/perf is stable if you decide to take it anyway. Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel