* [PATCH v3 0/7] arm64: dts: qcom: sa8775p: add more IOMMUs
@ 2023-04-11 12:59 Bartosz Golaszewski
2023-04-11 12:59 ` [PATCH v3 1/7] dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P Bartosz Golaszewski
` (7 more replies)
0 siblings, 8 replies; 13+ messages in thread
From: Bartosz Golaszewski @ 2023-04-11 12:59 UTC (permalink / raw)
To: Bjorn Andersson, Andy Gross, Konrad Dybcio, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Will Deacon,
Robin Murphy, Joerg Roedel, Catalin Marinas, Arnd Bergmann
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, iommu, Bartosz Golaszewski
From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Add the GPU and PCIe IOMMUs for sa8775p platforms as well as the required
GPU clock controller driver.
NOTE: I didn't pick up Krzysztof's tag for patch 4/7 as the patch changed
significantly.
v2 -> v3:
- select QCOM_GDSC in Kconfig for the GPUCC module
- the GPU SMMU is actually an adreno SMMU so describe it as such and
fix the DT
- fix the mapped memory size for the PCIe SMMU
v1 -> v2:
- remove unused include in the GPUCC driver
- remove unused clock from the GPUCC driver and make it compatible
with the generic QCom GPUCC bindings
- put the new defconfig option in the right place (as per savedefconfig)
and make the GPUCC driver a module rather than built-in
- describe the smmu clocks for sa8775p in dt-bindings
Bartosz Golaszewski (6):
dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P
arm64: defconfig: enable the SA8775P GPUCC driver
arm64: dts: qcom: sa8775p: add the pcie smmu node
arm64: dts: qcom: sa8775p: add the GPU clock controller node
dt-bindings: iommu: arm,smmu: enable clocks for sa8775p Adreno SMMU
arm64: dts: qcom: sa8775p: add the GPU IOMMU node
Shazad Hussain (1):
clk: qcom: add the GPUCC driver for sa8775p
.../devicetree/bindings/clock/qcom,gpucc.yaml | 2 +
.../devicetree/bindings/iommu/arm,smmu.yaml | 6 +-
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 125 ++++
arch/arm64/configs/defconfig | 1 +
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gpucc-sa8775p.c | 625 ++++++++++++++++++
.../dt-bindings/clock/qcom,sa8775p-gpucc.h | 50 ++
8 files changed, 817 insertions(+), 2 deletions(-)
create mode 100644 drivers/clk/qcom/gpucc-sa8775p.c
create mode 100644 include/dt-bindings/clock/qcom,sa8775p-gpucc.h
--
2.37.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH v3 1/7] dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P 2023-04-11 12:59 [PATCH v3 0/7] arm64: dts: qcom: sa8775p: add more IOMMUs Bartosz Golaszewski @ 2023-04-11 12:59 ` Bartosz Golaszewski 2023-04-11 12:59 ` [PATCH v3 2/7] clk: qcom: add the GPUCC driver for sa8775p Bartosz Golaszewski ` (6 subsequent siblings) 7 siblings, 0 replies; 13+ messages in thread From: Bartosz Golaszewski @ 2023-04-11 12:59 UTC (permalink / raw) To: Bjorn Andersson, Andy Gross, Konrad Dybcio, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Will Deacon, Robin Murphy, Joerg Roedel, Catalin Marinas, Arnd Bergmann Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-arm-kernel, iommu, Bartosz Golaszewski, Krzysztof Kozlowski From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Add the compatible for the Qualcomm Graphics Clock control module present on sa8775p platforms. It matches the generic QCom GPUCC description. Add device-specific DT bindings defines as well. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Stephen Boyd <sboyd@kernel.org> --- .../devicetree/bindings/clock/qcom,gpucc.yaml | 2 + .../dt-bindings/clock/qcom,sa8775p-gpucc.h | 50 +++++++++++++++++++ 2 files changed, 52 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,sa8775p-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml index db53eb288995..1e3dc9deded9 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml @@ -15,6 +15,7 @@ description: | See also:: include/dt-bindings/clock/qcom,gpucc-sdm845.h + include/dt-bindings/clock/qcom,gpucc-sa8775p.h include/dt-bindings/clock/qcom,gpucc-sc7180.h include/dt-bindings/clock/qcom,gpucc-sc7280.h include/dt-bindings/clock/qcom,gpucc-sc8280xp.h @@ -27,6 +28,7 @@ properties: compatible: enum: - qcom,sdm845-gpucc + - qcom,sa8775p-gpucc - qcom,sc7180-gpucc - qcom,sc7280-gpucc - qcom,sc8180x-gpucc diff --git a/include/dt-bindings/clock/qcom,sa8775p-gpucc.h b/include/dt-bindings/clock/qcom,sa8775p-gpucc.h new file mode 100644 index 000000000000..a5fd784b1ea2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sa8775p-gpucc.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPUCC_SA8775P_H +#define _DT_BINDINGS_CLK_QCOM_GPUCC_SA8775P_H + +/* GPU_CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL1 1 +#define GPU_CC_AHB_CLK 2 +#define GPU_CC_CB_CLK 3 +#define GPU_CC_CRC_AHB_CLK 4 +#define GPU_CC_CX_FF_CLK 5 +#define GPU_CC_CX_GMU_CLK 6 +#define GPU_CC_CX_SNOC_DVM_CLK 7 +#define GPU_CC_CXO_AON_CLK 8 +#define GPU_CC_CXO_CLK 9 +#define GPU_CC_DEMET_CLK 10 +#define GPU_CC_DEMET_DIV_CLK_SRC 11 +#define GPU_CC_FF_CLK_SRC 12 +#define GPU_CC_GMU_CLK_SRC 13 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14 +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 15 +#define GPU_CC_HUB_AON_CLK 16 +#define GPU_CC_HUB_CLK_SRC 17 +#define GPU_CC_HUB_CX_INT_CLK 18 +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 19 +#define GPU_CC_MEMNOC_GFX_CLK 20 +#define GPU_CC_SLEEP_CLK 21 +#define GPU_CC_XO_CLK_SRC 22 + +/* GPU_CC resets */ +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CB_BCR 1 +#define GPUCC_GPU_CC_CX_BCR 2 +#define GPUCC_GPU_CC_FAST_HUB_BCR 3 +#define GPUCC_GPU_CC_FF_BCR 4 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 5 +#define GPUCC_GPU_CC_GMU_BCR 6 +#define GPUCC_GPU_CC_GX_BCR 7 +#define GPUCC_GPU_CC_XO_BCR 8 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 +#define GPU_CC_GX_GDSC 1 + +#endif /* _DT_BINDINGS_CLK_QCOM_GPUCC_SA8775P_H */ -- 2.37.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v3 2/7] clk: qcom: add the GPUCC driver for sa8775p 2023-04-11 12:59 [PATCH v3 0/7] arm64: dts: qcom: sa8775p: add more IOMMUs Bartosz Golaszewski 2023-04-11 12:59 ` [PATCH v3 1/7] dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P Bartosz Golaszewski @ 2023-04-11 12:59 ` Bartosz Golaszewski 2023-04-11 12:59 ` [PATCH v3 3/7] arm64: defconfig: enable the SA8775P GPUCC driver Bartosz Golaszewski ` (5 subsequent siblings) 7 siblings, 0 replies; 13+ messages in thread From: Bartosz Golaszewski @ 2023-04-11 12:59 UTC (permalink / raw) To: Bjorn Andersson, Andy Gross, Konrad Dybcio, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Will Deacon, Robin Murphy, Joerg Roedel, Catalin Marinas, Arnd Bergmann Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-arm-kernel, iommu, Shazad Hussain, Bartosz Golaszewski From: Shazad Hussain <quic_shazhuss@quicinc.com> Add the clock driver for the Qualcomm Graphics Clock control module. Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> [Bartosz: make ready for upstream] Co-authored-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-sa8775p.c | 625 +++++++++++++++++++++++++++++++ 3 files changed, 635 insertions(+) create mode 100644 drivers/clk/qcom/gpucc-sa8775p.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index d71c9d6036bb..12be3e2371b3 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -445,6 +445,15 @@ config SA_GCC_8775P Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, UFS, SDCC, etc. +config SA_GPUCC_8775P + tristate "SA8775P Graphics clock controller" + select QCOM_GDSC + select SA_GCC_8775P + help + Support for the graphics clock controller on SA8775P devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config SC_GCC_7180 tristate "SC7180 Global Clock Controller" select QCOM_GDSC diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index b54085e579a0..9ff4c373ad95 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -72,6 +72,7 @@ obj-$(CONFIG_SC_DISPCC_7180) += dispcc-sc7180.o obj-$(CONFIG_SC_DISPCC_7280) += dispcc-sc7280.o obj-$(CONFIG_SC_DISPCC_8280XP) += dispcc-sc8280xp.o obj-$(CONFIG_SA_GCC_8775P) += gcc-sa8775p.o +obj-$(CONFIG_SA_GPUCC_8775P) += gpucc-sa8775p.o obj-$(CONFIG_SC_GCC_7180) += gcc-sc7180.o obj-$(CONFIG_SC_GCC_7280) += gcc-sc7280.o obj-$(CONFIG_SC_GCC_8180X) += gcc-sc8180x.o diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa8775p.c new file mode 100644 index 000000000000..18d23be8d435 --- /dev/null +++ b/drivers/clk/qcom/gpucc-sa8775p.c @@ -0,0 +1,625 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#include <linux/clk-provider.h> +#include <linux/err.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/of.h> +#include <linux/regmap.h> + +#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "reset.h" +#include "gdsc.h" + +/* Need to match the order of clocks in DT binding */ +enum { + DT_BI_TCXO, + DT_GCC_GPU_GPLL0_CLK_SRC, + DT_GCC_GPU_GPLL0_DIV_CLK_SRC, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL1_OUT_MAIN, +}; + +static const struct clk_parent_data parent_data_tcxo = { .index = DT_BI_TCXO }; + +static const struct pll_vco lucid_evo_vco[] = { + { 249600000, 2020000000, 0 }, +}; + +/* 810MHz configuration */ +static struct alpha_pll_config gpu_cc_pll0_config = { + .l = 0x2a, + .alpha = 0x3000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x32aa299c, + .user_ctl_val = 0x00000001, + .user_ctl_hi_val = 0x00400805, +}; + +static struct clk_alpha_pll gpu_cc_pll0 = { + .offset = 0x0, + .vco_table = lucid_evo_vco, + .num_vco = ARRAY_SIZE(lucid_evo_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr = { + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_pll0", + .parent_data = &parent_data_tcxo, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +/* 1000MHz configuration */ +static struct alpha_pll_config gpu_cc_pll1_config = { + .l = 0x34, + .alpha = 0x1555, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x32aa299c, + .user_ctl_val = 0x00000001, + .user_ctl_hi_val = 0x00400805, +}; + +static struct clk_alpha_pll gpu_cc_pll1 = { + .offset = 0x1000, + .vco_table = lucid_evo_vco, + .num_vco = ARRAY_SIZE(lucid_evo_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr = { + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_pll1", + .parent_data = &parent_data_tcxo, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, + { .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpu_cc_pll0.clkr.hw }, + { .hw = &gpu_cc_pll1.clkr.hw }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, + { .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC }, +}; + +static const struct parent_map gpu_cc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_2[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpu_cc_pll1.clkr.hw }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, + { .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC }, +}; + +static const struct parent_map gpu_cc_parent_map_3[] = { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_3[] = { + { .index = DT_BI_TCXO }, +}; + +static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_ff_clk_src = { + .cmd_rcgr = 0x9474, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_0, + .freq_tbl = ftbl_gpu_cc_ff_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_ff_clk_src", + .parent_data = gpu_cc_parent_data_0, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { + F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src = { + .cmd_rcgr = 0x9318, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_1, + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_gmu_clk_src", + .parent_data = gpu_cc_parent_data_1, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = { + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_hub_clk_src = { + .cmd_rcgr = 0x93ec, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_2, + .freq_tbl = ftbl_gpu_cc_hub_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_hub_clk_src", + .parent_data = gpu_cc_parent_data_2, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_2), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_xo_clk_src = { + .cmd_rcgr = 0x9010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_3, + .freq_tbl = ftbl_gpu_cc_xo_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_xo_clk_src", + .parent_data = gpu_cc_parent_data_3, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_3), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_demet_div_clk_src = { + .reg = 0x9054, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_demet_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = { + .reg = 0x9430, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_hub_ahb_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = { + .reg = 0x942c, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_hub_cx_int_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk = { + .halt_reg = 0x911c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x911c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_ahb_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cb_clk = { + .halt_reg = 0x93a4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x93a4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_cb_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk = { + .halt_reg = 0x9120, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9120, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_crc_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_ahb_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_ff_clk = { + .halt_reg = 0x914c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x914c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_cx_ff_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_ff_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk = { + .halt_reg = 0x913c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x913c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_cx_gmu_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { + .halt_reg = 0x9130, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9130, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_cx_snoc_dvm_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_aon_clk = { + .halt_reg = 0x9004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_cxo_aon_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk = { + .halt_reg = 0x9144, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9144, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_cxo_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_demet_clk = { + .halt_reg = 0x900c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x900c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_demet_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_demet_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { + .halt_reg = 0x7000, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_aon_clk = { + .halt_reg = 0x93e8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x93e8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_hub_aon_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_cx_int_clk = { + .halt_reg = 0x9148, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9148, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_hub_cx_int_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_cx_int_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_memnoc_gfx_clk = { + .halt_reg = 0x9150, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9150, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_memnoc_gfx_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk = { + .halt_reg = 0x9134, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9134, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_sleep_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *gpu_cc_sa8775p_clocks[] = { + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, + [GPU_CC_CB_CLK] = &gpu_cc_cb_clk.clkr, + [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr, + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, + [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, + [GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr, + [GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr, + [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr, + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, + [GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr, + [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr, + [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr, + [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr, + [GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr, + [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr, + [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, + [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, + [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, + [GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr, +}; + +static struct gdsc cx_gdsc = { + .gdscr = 0x9108, + .gds_hw_ctrl = 0x953c, + .pd = { + .name = "cx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE | RETAIN_FF_ENABLE | ALWAYS_ON, +}; + +static struct gdsc gx_gdsc = { + .gdscr = 0x905c, + .pd = { + .name = "gx_gdsc", + .power_on = gdsc_gx_do_nothing_enable, + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = AON_RESET | RETAIN_FF_ENABLE, +}; + +static struct gdsc *gpu_cc_sa8775p_gdscs[] = { + [GPU_CC_CX_GDSC] = &cx_gdsc, + [GPU_CC_GX_GDSC] = &gx_gdsc, +}; + +static const struct qcom_reset_map gpu_cc_sa8775p_resets[] = { + [GPUCC_GPU_CC_ACD_BCR] = { 0x9358 }, + [GPUCC_GPU_CC_CB_BCR] = { 0x93a0 }, + [GPUCC_GPU_CC_CX_BCR] = { 0x9104 }, + [GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 }, + [GPUCC_GPU_CC_FF_BCR] = { 0x9470 }, + [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 }, + [GPUCC_GPU_CC_GMU_BCR] = { 0x9314 }, + [GPUCC_GPU_CC_GX_BCR] = { 0x9058 }, + [GPUCC_GPU_CC_XO_BCR] = { 0x9000 }, +}; + +static const struct regmap_config gpu_cc_sa8775p_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x9988, + .fast_io = true, +}; + +static const struct qcom_cc_desc gpu_cc_sa8775p_desc = { + .config = &gpu_cc_sa8775p_regmap_config, + .clks = gpu_cc_sa8775p_clocks, + .num_clks = ARRAY_SIZE(gpu_cc_sa8775p_clocks), + .resets = gpu_cc_sa8775p_resets, + .num_resets = ARRAY_SIZE(gpu_cc_sa8775p_resets), + .gdscs = gpu_cc_sa8775p_gdscs, + .num_gdscs = ARRAY_SIZE(gpu_cc_sa8775p_gdscs), +}; + +static const struct of_device_id gpu_cc_sa8775p_match_table[] = { + { .compatible = "qcom,sa8775p-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_sa8775p_match_table); + +static int gpu_cc_sa8775p_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &gpu_cc_sa8775p_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); + clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); + + return qcom_cc_really_probe(pdev, &gpu_cc_sa8775p_desc, regmap); +} + +static struct platform_driver gpu_cc_sa8775p_driver = { + .probe = gpu_cc_sa8775p_probe, + .driver = { + .name = "gpu_cc-sa8775p", + .of_match_table = gpu_cc_sa8775p_match_table, + }, +}; + +static int __init gpu_cc_sa8775p_init(void) +{ + return platform_driver_register(&gpu_cc_sa8775p_driver); +} +subsys_initcall(gpu_cc_sa8775p_init); + +static void __exit gpu_cc_sa8775p_exit(void) +{ + platform_driver_unregister(&gpu_cc_sa8775p_driver); +} +module_exit(gpu_cc_sa8775p_exit); + +MODULE_DESCRIPTION("SA8775P GPUCC driver"); +MODULE_LICENSE("GPL"); -- 2.37.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v3 3/7] arm64: defconfig: enable the SA8775P GPUCC driver 2023-04-11 12:59 [PATCH v3 0/7] arm64: dts: qcom: sa8775p: add more IOMMUs Bartosz Golaszewski 2023-04-11 12:59 ` [PATCH v3 1/7] dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P Bartosz Golaszewski 2023-04-11 12:59 ` [PATCH v3 2/7] clk: qcom: add the GPUCC driver for sa8775p Bartosz Golaszewski @ 2023-04-11 12:59 ` Bartosz Golaszewski 2023-04-11 12:59 ` [PATCH v3 4/7] arm64: dts: qcom: sa8775p: add the pcie smmu node Bartosz Golaszewski ` (4 subsequent siblings) 7 siblings, 0 replies; 13+ messages in thread From: Bartosz Golaszewski @ 2023-04-11 12:59 UTC (permalink / raw) To: Bjorn Andersson, Andy Gross, Konrad Dybcio, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Will Deacon, Robin Murphy, Joerg Roedel, Catalin Marinas, Arnd Bergmann Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-arm-kernel, iommu, Bartosz Golaszewski From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Enable the GPUCC module for SA8775P platforms in the arm64 defconfig. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index b6342b40c600..e1063ab32658 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1164,6 +1164,7 @@ CONFIG_MSM_GCC_8998=y CONFIG_QCS_GCC_404=y CONFIG_SA_GCC_8775P=y CONFIG_SC_DISPCC_8280XP=m +CONFIG_SA_GPUCC_8775P=m CONFIG_SC_GCC_7180=y CONFIG_SC_GCC_7280=y CONFIG_SC_GCC_8180X=y -- 2.37.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v3 4/7] arm64: dts: qcom: sa8775p: add the pcie smmu node 2023-04-11 12:59 [PATCH v3 0/7] arm64: dts: qcom: sa8775p: add more IOMMUs Bartosz Golaszewski ` (2 preceding siblings ...) 2023-04-11 12:59 ` [PATCH v3 3/7] arm64: defconfig: enable the SA8775P GPUCC driver Bartosz Golaszewski @ 2023-04-11 12:59 ` Bartosz Golaszewski 2023-04-11 12:59 ` [PATCH v3 5/7] arm64: dts: qcom: sa8775p: add the GPU clock controller node Bartosz Golaszewski ` (3 subsequent siblings) 7 siblings, 0 replies; 13+ messages in thread From: Bartosz Golaszewski @ 2023-04-11 12:59 UTC (permalink / raw) To: Bjorn Andersson, Andy Gross, Konrad Dybcio, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Will Deacon, Robin Murphy, Joerg Roedel, Catalin Marinas, Arnd Bergmann Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-arm-kernel, iommu, Bartosz Golaszewski From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Add the PCIe SMMU node for sa8775p platforms. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 74 +++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 2343df7e0ea4..a23175352a20 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -809,6 +809,80 @@ apps_smmu: iommu@15000000 { <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>; }; + pcie_smmu: iommu@15200000 { + compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x15200000 0x0 0x80000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + + interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ -- 2.37.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v3 5/7] arm64: dts: qcom: sa8775p: add the GPU clock controller node 2023-04-11 12:59 [PATCH v3 0/7] arm64: dts: qcom: sa8775p: add more IOMMUs Bartosz Golaszewski ` (3 preceding siblings ...) 2023-04-11 12:59 ` [PATCH v3 4/7] arm64: dts: qcom: sa8775p: add the pcie smmu node Bartosz Golaszewski @ 2023-04-11 12:59 ` Bartosz Golaszewski 2023-04-11 12:59 ` [PATCH v3 6/7] dt-bindings: iommu: arm,smmu: enable clocks for sa8775p Adreno SMMU Bartosz Golaszewski ` (2 subsequent siblings) 7 siblings, 0 replies; 13+ messages in thread From: Bartosz Golaszewski @ 2023-04-11 12:59 UTC (permalink / raw) To: Bjorn Andersson, Andy Gross, Konrad Dybcio, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Will Deacon, Robin Murphy, Joerg Roedel, Catalin Marinas, Arnd Bergmann Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-arm-kernel, iommu, Bartosz Golaszewski From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Add the GPUCC node for sa8775p platforms. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index a23175352a20..191b510b5a1a 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -591,6 +591,20 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + gpucc: clock-controller@3d90000 { + compatible = "qcom,sa8775p-gpucc"; + reg = <0x0 0x03d90000 0x0 0xa000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sa8775p-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x30000>, -- 2.37.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v3 6/7] dt-bindings: iommu: arm,smmu: enable clocks for sa8775p Adreno SMMU 2023-04-11 12:59 [PATCH v3 0/7] arm64: dts: qcom: sa8775p: add more IOMMUs Bartosz Golaszewski ` (4 preceding siblings ...) 2023-04-11 12:59 ` [PATCH v3 5/7] arm64: dts: qcom: sa8775p: add the GPU clock controller node Bartosz Golaszewski @ 2023-04-11 12:59 ` Bartosz Golaszewski 2023-04-12 7:16 ` Krzysztof Kozlowski 2023-04-11 12:59 ` [PATCH v3 7/7] arm64: dts: qcom: sa8775p: add the GPU IOMMU node Bartosz Golaszewski 2023-04-14 3:37 ` (subset) [PATCH v3 0/7] arm64: dts: qcom: sa8775p: add more IOMMUs Bjorn Andersson 7 siblings, 1 reply; 13+ messages in thread From: Bartosz Golaszewski @ 2023-04-11 12:59 UTC (permalink / raw) To: Bjorn Andersson, Andy Gross, Konrad Dybcio, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Will Deacon, Robin Murphy, Joerg Roedel, Catalin Marinas, Arnd Bergmann Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-arm-kernel, iommu, Bartosz Golaszewski From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> The GPU SMMU will require the clocks property to be set so put the relevant compatible into the adreno if-then block. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 807cb511fe18..d966dc65ce10 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -79,6 +79,7 @@ properties: - description: Qcom Adreno GPUs implementing "arm,smmu-500" items: - enum: + - qcom,sa8775p-smmu-500 - qcom,sc7280-smmu-500 - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 @@ -317,7 +318,9 @@ allOf: properties: compatible: contains: - const: qcom,sc7280-smmu-500 + enum: + - qcom,sa8775p-smmu-500 + - qcom,sc7280-smmu-500 then: properties: clock-names: @@ -375,7 +378,6 @@ allOf: - nvidia,smmu-500 - qcom,qcm2290-smmu-500 - qcom,qdu1000-smmu-500 - - qcom,sa8775p-smmu-500 - qcom,sc7180-smmu-500 - qcom,sc8180x-smmu-500 - qcom,sc8280xp-smmu-500 -- 2.37.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v3 6/7] dt-bindings: iommu: arm,smmu: enable clocks for sa8775p Adreno SMMU 2023-04-11 12:59 ` [PATCH v3 6/7] dt-bindings: iommu: arm,smmu: enable clocks for sa8775p Adreno SMMU Bartosz Golaszewski @ 2023-04-12 7:16 ` Krzysztof Kozlowski 0 siblings, 0 replies; 13+ messages in thread From: Krzysztof Kozlowski @ 2023-04-12 7:16 UTC (permalink / raw) To: Bartosz Golaszewski, Bjorn Andersson, Andy Gross, Konrad Dybcio, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Will Deacon, Robin Murphy, Joerg Roedel, Catalin Marinas, Arnd Bergmann Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-arm-kernel, iommu, Bartosz Golaszewski On 11/04/2023 14:59, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > The GPU SMMU will require the clocks property to be set so put the > relevant compatible into the adreno if-then block. > > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > --- This is a friendly reminder during the review process. It looks like you received a tag and forgot to add it. If you do not know the process, here is a short explanation: Please add Acked-by/Reviewed-by/Tested-by tags when posting new versions. However, there's no need to repost patches *only* to add the tags. The upstream maintainer will do that for acks received on the version they apply. https://elixir.bootlin.com/linux/v5.17/source/Documentation/process/submitting-patches.rst#L540 If a tag was not added on purpose, please state why and what changed. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v3 7/7] arm64: dts: qcom: sa8775p: add the GPU IOMMU node 2023-04-11 12:59 [PATCH v3 0/7] arm64: dts: qcom: sa8775p: add more IOMMUs Bartosz Golaszewski ` (5 preceding siblings ...) 2023-04-11 12:59 ` [PATCH v3 6/7] dt-bindings: iommu: arm,smmu: enable clocks for sa8775p Adreno SMMU Bartosz Golaszewski @ 2023-04-11 12:59 ` Bartosz Golaszewski 2023-04-11 13:16 ` Konrad Dybcio 2023-04-14 3:37 ` (subset) [PATCH v3 0/7] arm64: dts: qcom: sa8775p: add more IOMMUs Bjorn Andersson 7 siblings, 1 reply; 13+ messages in thread From: Bartosz Golaszewski @ 2023-04-11 12:59 UTC (permalink / raw) To: Bjorn Andersson, Andy Gross, Konrad Dybcio, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Will Deacon, Robin Murphy, Joerg Roedel, Catalin Marinas, Arnd Bergmann Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-arm-kernel, iommu, Bartosz Golaszewski From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Add the Adreno GPU IOMMU for sa8775p-based platforms. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 37 +++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 191b510b5a1a..11f3d80dd869 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -7,6 +7,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,sa8775p-gcc.h> +#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> @@ -605,6 +606,42 @@ gpucc: clock-controller@3d90000 { #power-domain-cells = <1>; }; + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu", + "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x20000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + dma-coherent; + power-domains = <&gpucc GPU_CC_CX_GDSC>; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>; + clock-names = "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk", + "gpu_cc_hlos1_vote_gpu_smmu_clk", + "gpu_cc_cx_gmu_clk", + "gpu_cc_hub_cx_int_clk", + "gpu_cc_hub_aon_clk"; + interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sa8775p-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x30000>, -- 2.37.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v3 7/7] arm64: dts: qcom: sa8775p: add the GPU IOMMU node 2023-04-11 12:59 ` [PATCH v3 7/7] arm64: dts: qcom: sa8775p: add the GPU IOMMU node Bartosz Golaszewski @ 2023-04-11 13:16 ` Konrad Dybcio 2023-04-11 14:41 ` Bartosz Golaszewski 0 siblings, 1 reply; 13+ messages in thread From: Konrad Dybcio @ 2023-04-11 13:16 UTC (permalink / raw) To: Bartosz Golaszewski, Bjorn Andersson, Andy Gross, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Will Deacon, Robin Murphy, Joerg Roedel, Catalin Marinas, Arnd Bergmann Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-arm-kernel, iommu, Bartosz Golaszewski On 11.04.2023 14:59, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > Add the Adreno GPU IOMMU for sa8775p-based platforms. > > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > --- > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 37 +++++++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > index 191b510b5a1a..11f3d80dd869 100644 > --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi > +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > @@ -7,6 +7,7 @@ > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/clock/qcom,rpmh.h> > #include <dt-bindings/clock/qcom,sa8775p-gcc.h> > +#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> > #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> > #include <dt-bindings/power/qcom-rpmpd.h> > #include <dt-bindings/soc/qcom,rpmh-rsc.h> > @@ -605,6 +606,42 @@ gpucc: clock-controller@3d90000 { > #power-domain-cells = <1>; > }; > > + adreno_smmu: iommu@3da0000 { > + compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu", > + "arm,mmu-500"; Err.. does it even boot like this? You dropped the qcom,smmu-500 compatible which means it's getting bound to the generic SMMU driver (without QC quirks). If that was a mistake, you should have had all 4 "qcom,sa8775p-smmu-500", qcom,adreno-smmu, "qcom,smmu-500", "arm,mmu-500" Without falling into the qc-specific codepaths, the Adreno compat does nothing. Konrad > + reg = <0x0 0x03da0000 0x0 0x20000>; > + #iommu-cells = <2>; > + #global-interrupts = <2>; > + dma-coherent; > + power-domains = <&gpucc GPU_CC_CX_GDSC>; > + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, > + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, > + <&gpucc GPU_CC_AHB_CLK>, > + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, > + <&gpucc GPU_CC_CX_GMU_CLK>, > + <&gpucc GPU_CC_HUB_CX_INT_CLK>, > + <&gpucc GPU_CC_HUB_AON_CLK>; > + clock-names = "gcc_gpu_memnoc_gfx_clk", > + "gcc_gpu_snoc_dvm_gfx_clk", > + "gpu_cc_ahb_clk", > + "gpu_cc_hlos1_vote_gpu_smmu_clk", > + "gpu_cc_cx_gmu_clk", > + "gpu_cc_hub_cx_int_clk", > + "gpu_cc_hub_aon_clk"; > + interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > pdc: interrupt-controller@b220000 { > compatible = "qcom,sa8775p-pdc", "qcom,pdc"; > reg = <0x0 0x0b220000 0x0 0x30000>, _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v3 7/7] arm64: dts: qcom: sa8775p: add the GPU IOMMU node 2023-04-11 13:16 ` Konrad Dybcio @ 2023-04-11 14:41 ` Bartosz Golaszewski 2023-04-11 19:50 ` Konrad Dybcio 0 siblings, 1 reply; 13+ messages in thread From: Bartosz Golaszewski @ 2023-04-11 14:41 UTC (permalink / raw) To: Konrad Dybcio Cc: Bjorn Andersson, Andy Gross, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Will Deacon, Robin Murphy, Joerg Roedel, Catalin Marinas, Arnd Bergmann, linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-arm-kernel, iommu, Bartosz Golaszewski On Tue, Apr 11, 2023 at 3:16 PM Konrad Dybcio <konrad.dybcio@linaro.org> wrote: > > > > On 11.04.2023 14:59, Bartosz Golaszewski wrote: > > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > > > Add the Adreno GPU IOMMU for sa8775p-based platforms. > > > > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > --- > > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 37 +++++++++++++++++++++++++++ > > 1 file changed, 37 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > > index 191b510b5a1a..11f3d80dd869 100644 > > --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > > @@ -7,6 +7,7 @@ > > #include <dt-bindings/interrupt-controller/arm-gic.h> > > #include <dt-bindings/clock/qcom,rpmh.h> > > #include <dt-bindings/clock/qcom,sa8775p-gcc.h> > > +#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> > > #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> > > #include <dt-bindings/power/qcom-rpmpd.h> > > #include <dt-bindings/soc/qcom,rpmh-rsc.h> > > @@ -605,6 +606,42 @@ gpucc: clock-controller@3d90000 { > > #power-domain-cells = <1>; > > }; > > > > + adreno_smmu: iommu@3da0000 { > > + compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu", > > + "arm,mmu-500"; > Err.. does it even boot like this? You dropped the qcom,smmu-500 compatible > which means it's getting bound to the generic SMMU driver (without > QC quirks). If that was a mistake, you should have had all 4 > > "qcom,sa8775p-smmu-500", qcom,adreno-smmu, "qcom,smmu-500", "arm,mmu-500" > > Without falling into the qc-specific codepaths, the Adreno compat does > nothing. > I did that initially, then noticed dtbs_check fails because the existing adreno GPUs implementing "arm,smmu-500" expect three compatibles like in this commit. I did that and the driver still probed the same so I assumed all's good. You're right of course, the adreno impl is not being assigned without "qcom,smmu-500". Are the bindings wrong in this case and should it be something like the following? diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index d966dc65ce10..cd1b052a7242 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -84,6 +84,7 @@ properties: - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 - const: qcom,adreno-smmu + - const: qcom,smmu-500 - const: arm,mmu-500 - description: Qcom Adreno GPUs implementing "arm,smmu-v2" items: Bartosz > Konrad > > + reg = <0x0 0x03da0000 0x0 0x20000>; > > + #iommu-cells = <2>; > > + #global-interrupts = <2>; > > + dma-coherent; > > + power-domains = <&gpucc GPU_CC_CX_GDSC>; > > + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, > > + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, > > + <&gpucc GPU_CC_AHB_CLK>, > > + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, > > + <&gpucc GPU_CC_CX_GMU_CLK>, > > + <&gpucc GPU_CC_HUB_CX_INT_CLK>, > > + <&gpucc GPU_CC_HUB_AON_CLK>; > > + clock-names = "gcc_gpu_memnoc_gfx_clk", > > + "gcc_gpu_snoc_dvm_gfx_clk", > > + "gpu_cc_ahb_clk", > > + "gpu_cc_hlos1_vote_gpu_smmu_clk", > > + "gpu_cc_cx_gmu_clk", > > + "gpu_cc_hub_cx_int_clk", > > + "gpu_cc_hub_aon_clk"; > > + interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + > > pdc: interrupt-controller@b220000 { > > compatible = "qcom,sa8775p-pdc", "qcom,pdc"; > > reg = <0x0 0x0b220000 0x0 0x30000>, _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v3 7/7] arm64: dts: qcom: sa8775p: add the GPU IOMMU node 2023-04-11 14:41 ` Bartosz Golaszewski @ 2023-04-11 19:50 ` Konrad Dybcio 0 siblings, 0 replies; 13+ messages in thread From: Konrad Dybcio @ 2023-04-11 19:50 UTC (permalink / raw) To: Bartosz Golaszewski Cc: Bjorn Andersson, Andy Gross, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Will Deacon, Robin Murphy, Joerg Roedel, Catalin Marinas, Arnd Bergmann, linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-arm-kernel, iommu, Bartosz Golaszewski On 11.04.2023 16:41, Bartosz Golaszewski wrote: > On Tue, Apr 11, 2023 at 3:16 PM Konrad Dybcio <konrad.dybcio@linaro.org> wrote: >> >> >> >> On 11.04.2023 14:59, Bartosz Golaszewski wrote: >>> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> >>> >>> Add the Adreno GPU IOMMU for sa8775p-based platforms. >>> >>> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> >>> --- >>> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 37 +++++++++++++++++++++++++++ >>> 1 file changed, 37 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi >>> index 191b510b5a1a..11f3d80dd869 100644 >>> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi >>> @@ -7,6 +7,7 @@ >>> #include <dt-bindings/interrupt-controller/arm-gic.h> >>> #include <dt-bindings/clock/qcom,rpmh.h> >>> #include <dt-bindings/clock/qcom,sa8775p-gcc.h> >>> +#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> >>> #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> >>> #include <dt-bindings/power/qcom-rpmpd.h> >>> #include <dt-bindings/soc/qcom,rpmh-rsc.h> >>> @@ -605,6 +606,42 @@ gpucc: clock-controller@3d90000 { >>> #power-domain-cells = <1>; >>> }; >>> >>> + adreno_smmu: iommu@3da0000 { >>> + compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu", >>> + "arm,mmu-500"; >> Err.. does it even boot like this? You dropped the qcom,smmu-500 compatible >> which means it's getting bound to the generic SMMU driver (without >> QC quirks). If that was a mistake, you should have had all 4 >> >> "qcom,sa8775p-smmu-500", qcom,adreno-smmu, "qcom,smmu-500", "arm,mmu-500" >> >> Without falling into the qc-specific codepaths, the Adreno compat does >> nothing. >> > > I did that initially, then noticed dtbs_check fails because the > existing adreno GPUs implementing "arm,smmu-500" expect three > compatibles like in this commit. I did that and the driver still > probed the same so I assumed all's good. You're right of course, the > adreno impl is not being assigned without "qcom,smmu-500". Are the > bindings wrong in this case and should it be something like the > following? > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > index d966dc65ce10..cd1b052a7242 100644 > --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > @@ -84,6 +84,7 @@ properties: > - qcom,sm8150-smmu-500 > - qcom,sm8250-smmu-500 > - const: qcom,adreno-smmu > + - const: qcom,smmu-500 > - const: arm,mmu-500 > - description: Qcom Adreno GPUs implementing "arm,smmu-v2" > items: > > Bartosz Check https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/commit/?h=for-joerg/arm-smmu/bindings&id=5c3686616b1840b3143b227eb58fb1c1621d204e Konrad > >> Konrad >>> + reg = <0x0 0x03da0000 0x0 0x20000>; >>> + #iommu-cells = <2>; >>> + #global-interrupts = <2>; >>> + dma-coherent; >>> + power-domains = <&gpucc GPU_CC_CX_GDSC>; >>> + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, >>> + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, >>> + <&gpucc GPU_CC_AHB_CLK>, >>> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, >>> + <&gpucc GPU_CC_CX_GMU_CLK>, >>> + <&gpucc GPU_CC_HUB_CX_INT_CLK>, >>> + <&gpucc GPU_CC_HUB_AON_CLK>; >>> + clock-names = "gcc_gpu_memnoc_gfx_clk", >>> + "gcc_gpu_snoc_dvm_gfx_clk", >>> + "gpu_cc_ahb_clk", >>> + "gpu_cc_hlos1_vote_gpu_smmu_clk", >>> + "gpu_cc_cx_gmu_clk", >>> + "gpu_cc_hub_cx_int_clk", >>> + "gpu_cc_hub_aon_clk"; >>> + interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; >>> + }; >>> + >>> pdc: interrupt-controller@b220000 { >>> compatible = "qcom,sa8775p-pdc", "qcom,pdc"; >>> reg = <0x0 0x0b220000 0x0 0x30000>, _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: (subset) [PATCH v3 0/7] arm64: dts: qcom: sa8775p: add more IOMMUs 2023-04-11 12:59 [PATCH v3 0/7] arm64: dts: qcom: sa8775p: add more IOMMUs Bartosz Golaszewski ` (6 preceding siblings ...) 2023-04-11 12:59 ` [PATCH v3 7/7] arm64: dts: qcom: sa8775p: add the GPU IOMMU node Bartosz Golaszewski @ 2023-04-14 3:37 ` Bjorn Andersson 7 siblings, 0 replies; 13+ messages in thread From: Bjorn Andersson @ 2023-04-14 3:37 UTC (permalink / raw) To: Will Deacon, Stephen Boyd, Bartosz Golaszewski, Andy Gross, Konrad Dybcio, Rob Herring, Joerg Roedel, Catalin Marinas, Robin Murphy, Arnd Bergmann, Krzysztof Kozlowski, Michael Turquette Cc: iommu, linux-arm-msm, Bartosz Golaszewski, linux-clk, linux-arm-kernel, devicetree, linux-kernel On Tue, 11 Apr 2023 14:59:03 +0200, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > Add the GPU and PCIe IOMMUs for sa8775p platforms as well as the required > GPU clock controller driver. > > NOTE: I didn't pick up Krzysztof's tag for patch 4/7 as the patch changed > significantly. > > [...] Applied, thanks! [1/7] dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P commit: daa9e76d17570cdd2dbec28244e60e2cb0eafb36 [2/7] clk: qcom: add the GPUCC driver for sa8775p commit: 0afa16afc36d0e462c7f815b0131d2e9013849ac Best regards, -- Bjorn Andersson <andersson@kernel.org> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2023-04-14 3:34 UTC | newest] Thread overview: 13+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-04-11 12:59 [PATCH v3 0/7] arm64: dts: qcom: sa8775p: add more IOMMUs Bartosz Golaszewski 2023-04-11 12:59 ` [PATCH v3 1/7] dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P Bartosz Golaszewski 2023-04-11 12:59 ` [PATCH v3 2/7] clk: qcom: add the GPUCC driver for sa8775p Bartosz Golaszewski 2023-04-11 12:59 ` [PATCH v3 3/7] arm64: defconfig: enable the SA8775P GPUCC driver Bartosz Golaszewski 2023-04-11 12:59 ` [PATCH v3 4/7] arm64: dts: qcom: sa8775p: add the pcie smmu node Bartosz Golaszewski 2023-04-11 12:59 ` [PATCH v3 5/7] arm64: dts: qcom: sa8775p: add the GPU clock controller node Bartosz Golaszewski 2023-04-11 12:59 ` [PATCH v3 6/7] dt-bindings: iommu: arm,smmu: enable clocks for sa8775p Adreno SMMU Bartosz Golaszewski 2023-04-12 7:16 ` Krzysztof Kozlowski 2023-04-11 12:59 ` [PATCH v3 7/7] arm64: dts: qcom: sa8775p: add the GPU IOMMU node Bartosz Golaszewski 2023-04-11 13:16 ` Konrad Dybcio 2023-04-11 14:41 ` Bartosz Golaszewski 2023-04-11 19:50 ` Konrad Dybcio 2023-04-14 3:37 ` (subset) [PATCH v3 0/7] arm64: dts: qcom: sa8775p: add more IOMMUs Bjorn Andersson
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).