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From: Radu Rendec <rrendec@redhat.com>
To: linux-kernel@vger.kernel.org
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>,
	Pierre Gondois <Pierre.Gondois@arm.com>,
	Sudeep Holla <sudeep.holla@arm.com>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 3/3] cacheinfo: Allow early level detection when DT/ACPI info is missing/broken
Date: Wed, 12 Apr 2023 14:57:59 -0400	[thread overview]
Message-ID: <20230412185759.755408-4-rrendec@redhat.com> (raw)
In-Reply-To: <20230412185759.755408-1-rrendec@redhat.com>

Recent work enables cacheinfo memory for secondary CPUs to be allocated
early, while still running on the primary CPU. That allows cacheinfo
memory to be allocated safely on RT kernels. To make that work, the
number of cache levels/leaves must be defined in the device tree or ACPI
tables. Further work adds a path for early detection of the number of
cache levels/leaves, which makes it possible to allocate the cacheinfo
memory early without requiring extra DT/ACPI information.

This patch addresses a specific issue with ACPI systems with no PPTT. In
that case, parse_acpi_topology() returns an error code, which in turn
makes init_cpu_topology() return early, before fetch_cache_info() is
called. In that case, the early cache level detection doesn't run.

The solution is to simply remove the "return" statement and let the code
flow fall through to calling fetch_cache_info().

Signed-off-by: Radu Rendec <rrendec@redhat.com>
Reported-by: Pierre Gondois <pierre.gondois@arm.com>
Link: https://lore.kernel.org/all/dea94484-797f-3034-7b86-6d88801c0d91@arm.com/
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
---
 drivers/base/arch_topology.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c
index b1c1dd38ab01..147fb7d4af96 100644
--- a/drivers/base/arch_topology.c
+++ b/drivers/base/arch_topology.c
@@ -835,10 +835,10 @@ void __init init_cpu_topology(void)
 	if (ret) {
 		/*
 		 * Discard anything that was parsed if we hit an error so we
-		 * don't use partial information.
+		 * don't use partial information. But do not return yet to give
+		 * arch-specific early cache level detection a chance to run.
 		 */
 		reset_cpu_topology();
-		return;
 	}
 
 	for_each_possible_cpu(cpu) {
-- 
2.39.2


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  parent reply	other threads:[~2023-04-12 19:00 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-12 18:57 [PATCH v4 0/3] arch_topology: Pre-allocate cacheinfo from primary CPU Radu Rendec
2023-04-12 18:57 ` [PATCH v4 1/3] cacheinfo: Add arch specific early level initializer Radu Rendec
     [not found]   ` <20230510191207.GA18514@ranerica-svr.sc.intel.com>
2023-05-15  9:36     ` Sudeep Holla
2023-05-18  1:27       ` Ricardo Neri
2023-05-18  9:34         ` Sudeep Holla
2023-05-31 12:22           ` Sudeep Holla
2023-05-31 17:03             ` Ricardo Neri
2023-08-07 23:23               ` Ricardo Neri
     [not found]     ` <b49e241d3ea8c679b81134e22c908ca64aeca18c.camel@redhat.com>
     [not found]       ` <20230511000058.GD18514@ranerica-svr.sc.intel.com>
     [not found]         ` <9020807789b70db0d84d142cbfed2bd8868f366a.camel@redhat.com>
2023-05-19 21:44           ` Ricardo Neri
2023-05-19 22:02             ` Radu Rendec
2023-04-12 18:57 ` [PATCH v4 2/3] cacheinfo: Add arm64 early level initializer implementation Radu Rendec
2023-04-13 10:22   ` Sudeep Holla
2023-04-13 14:45     ` Will Deacon
2023-04-13 15:05       ` Sudeep Holla
2023-04-14 12:46         ` Will Deacon
2023-04-12 18:57 ` Radu Rendec [this message]
2023-04-17 14:07 ` [PATCH v4 0/3] arch_topology: Pre-allocate cacheinfo from primary CPU Sudeep Holla

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