From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 28714C77B61 for ; Thu, 13 Apr 2023 10:23:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=dbR0eCL2QA4B1Ky044lxpQHTkn1LSHmHggQJ3YThbsc=; b=j1/NaVACZb94ue HOc7RMjSMYA0IIuAOxE7tEt+4fO/8xjljfdagJWPphsCdnZygplwvAxxO8BZUp8kLzM0e97HPYxAZ iNf8al/2H0wUUB7KRCZXhIxUG7Ap8YbWQ2u7IQ6kEujbHVshZAJcZSm+ZCMlufe6EoniKw2e9CNrv fecGNV/wXlEwT88FGw9dpIH5dVnR3SQL5zACanC0dUmtTAwo1hFmC09sntD0qFR5aSE1Y7LBGisGs tfcrtqfT9lf2jSDNx/kgVabJe0XkuIBXY8nZabr2fxGkhIG71qC18WQXGM6hZ4vDMRioMC0LFyTJg d+JOHDJmJY3xWMvSr5Ow==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pmu6E-005l8w-0I; Thu, 13 Apr 2023 10:22:42 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pmu6A-005l6Y-2n for linux-arm-kernel@lists.infradead.org; Thu, 13 Apr 2023 10:22:40 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 82FE2153B; Thu, 13 Apr 2023 03:23:14 -0700 (PDT) Received: from bogus (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2E3B73F6C4; Thu, 13 Apr 2023 03:22:29 -0700 (PDT) Date: Thu, 13 Apr 2023 11:22:26 +0100 From: Sudeep Holla To: Radu Rendec , Will Deacon Cc: linux-kernel@vger.kernel.org, Catalin Marinas , Pierre Gondois , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v4 2/3] cacheinfo: Add arm64 early level initializer implementation Message-ID: <20230413102226.yzzd6iccqeamheas@bogus> References: <20230412185759.755408-1-rrendec@redhat.com> <20230412185759.755408-3-rrendec@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230412185759.755408-3-rrendec@redhat.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230413_032238_977255_26FC4F30 X-CRM114-Status: GOOD ( 19.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Will, On Wed, Apr 12, 2023 at 02:57:58PM -0400, Radu Rendec wrote: > This patch adds an architecture specific early cache level detection > handler for arm64. This is basically the CLIDR_EL1 based detection that > was previously done (only) in init_cache_level(). > > This is part of a patch series that attempts to further the work in > commit 5944ce092b97 ("arch_topology: Build cacheinfo from primary CPU"). > Previously, in the absence of any DT/ACPI cache info, architecture > specific cache detection and info allocation for secondary CPUs would > happen in non-preemptible context during early CPU initialization and > trigger a "BUG: sleeping function called from invalid context" splat on > an RT kernel. > > This patch does not solve the problem completely for RT kernels. It > relies on the assumption that on most systems, the CPUs are symmetrical > and therefore have the same number of cache leaves. The cacheinfo memory > is allocated early (on the primary CPU), relying on the new handler. If > later (when CLIDR_EL1 based detection runs again on the secondary CPU) > the initial assumption proves to be wrong and the CPU has in fact more > leaves, the cacheinfo memory is reallocated, and that still triggers a > splat on an RT kernel. > > In other words, asymmetrical CPU systems *must* still provide cacheinfo > data in DT/ACPI to avoid the splat on RT kernels (unless secondary CPUs > happen to have less leaves than the primary CPU). But symmetrical CPU > systems (the majority) can now get away without the additional DT/ACPI > data and rely on CLIDR_EL1 based detection. > If you are okay with the change, can I have your Acked-by, so that I can route this via Greg's tree ? -- Regards, Sudeep _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel