From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0A7C4C77B61 for ; Thu, 13 Apr 2023 14:46:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+1Z1UNpYea6P4pAsPiZsnV1Q6jrkKbI2iyWQyskLFYA=; b=LZqqzoEvlQ9yv1 0H33CYKKlRinprDHewpQ34n9VHlkAeg7X/s6OuInYmtMYgI2RF0EIQp5B/DIBel5XGdv2m0euhUzc 6SrhaQr6YYBUYeJtUO7jJoKRt3By4EZYf7O3OraCUlszmFBEaUgvCXAQ9XAZJMjrNcKlbqOdaWzUB moXYoM9UsH9PgOvikhdIFSfrolYD9Dztjl8d1xao7yMoJomnRwOY6CBLZAk5B2AsDo2lapjvxcFyt S8JuWTprcMy6LadrYS9yqK0YNK3daIDmoAtxkheosLkwitT5F7ZvfdSKPTR76KJVL21Zo76tgEDQo D8mfV5omO65KIqM63OHw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pmyCY-006Qs6-1R; Thu, 13 Apr 2023 14:45:30 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pmyCW-006QrY-0y for linux-arm-kernel@lists.infradead.org; Thu, 13 Apr 2023 14:45:29 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A2500636A4; Thu, 13 Apr 2023 14:45:27 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DDA5EC433EF; Thu, 13 Apr 2023 14:45:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1681397127; bh=xrdv4Z7PA0F+WTeFeKIaPEng4KjDHdC2Dt/i176IcB4=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=MPM2nFoFiNNXItqdew/HTsNfivJl5f79eXUDzgdTldb6se9vsz4u1gh59Fdm4k5Hg Xizy9eZJOmzJERDdtBDAM4mWUo0UAeFuFZe+1uw5/AaMZRxoR+1HQDqVYuVHzRjgmD SHc/gVfZqs43RxNrm15jvGqGGqzfVPtxRcRYRe/goJHTZRsRUjXxfCSvNzFaH7M6bt yvvTcp4IpGWRDW1NiirrROj731r3X7EfnbhzMr2fnSotD/SKyqr2kMiPaFHOFAEdMP Xpu05z37iYesguUL+RLEt4oN3tSDJmeUKXZH3gprSrLcaSAQtIFF8ZsTJ1+dE641N4 fYuAz8PrgiHQQ== Date: Thu, 13 Apr 2023 15:45:22 +0100 From: Will Deacon To: Sudeep Holla Cc: Radu Rendec , linux-kernel@vger.kernel.org, Catalin Marinas , Pierre Gondois , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v4 2/3] cacheinfo: Add arm64 early level initializer implementation Message-ID: <20230413144519.GA26421@willie-the-truck> References: <20230412185759.755408-1-rrendec@redhat.com> <20230412185759.755408-3-rrendec@redhat.com> <20230413102226.yzzd6iccqeamheas@bogus> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230413102226.yzzd6iccqeamheas@bogus> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230413_074528_376219_C8BE1E3F X-CRM114-Status: GOOD ( 29.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Apr 13, 2023 at 11:22:26AM +0100, Sudeep Holla wrote: > Hi Will, > > On Wed, Apr 12, 2023 at 02:57:58PM -0400, Radu Rendec wrote: > > This patch adds an architecture specific early cache level detection > > handler for arm64. This is basically the CLIDR_EL1 based detection that > > was previously done (only) in init_cache_level(). > > > > This is part of a patch series that attempts to further the work in > > commit 5944ce092b97 ("arch_topology: Build cacheinfo from primary CPU"). > > Previously, in the absence of any DT/ACPI cache info, architecture > > specific cache detection and info allocation for secondary CPUs would > > happen in non-preemptible context during early CPU initialization and > > trigger a "BUG: sleeping function called from invalid context" splat on > > an RT kernel. > > > > This patch does not solve the problem completely for RT kernels. It > > relies on the assumption that on most systems, the CPUs are symmetrical > > and therefore have the same number of cache leaves. The cacheinfo memory > > is allocated early (on the primary CPU), relying on the new handler. If > > later (when CLIDR_EL1 based detection runs again on the secondary CPU) > > the initial assumption proves to be wrong and the CPU has in fact more > > leaves, the cacheinfo memory is reallocated, and that still triggers a > > splat on an RT kernel. > > > > In other words, asymmetrical CPU systems *must* still provide cacheinfo > > data in DT/ACPI to avoid the splat on RT kernels (unless secondary CPUs > > happen to have less leaves than the primary CPU). But symmetrical CPU > > systems (the majority) can now get away without the additional DT/ACPI > > data and rely on CLIDR_EL1 based detection. > > > > If you are okay with the change, can I have your Acked-by, so that I can > route this via Greg's tree ? I really dislike the profileration of __weak functions in this file, rather than the usual approach of having arch-specific static inlines in a header file but it seems that nobody has the appetite to clean that up :( So I'm fine for Greg to queue this if he wants to, but I'd be a lot more excited if somebody tidied things up a bit first. Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel