From: Jayesh Choudhary <j-choudhary@ti.com>
To: <nm@ti.com>, <vigneshr@ti.com>, <afd@ti.com>
Cc: <s-vadapalli@ti.com>, <kristo@kernel.org>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>,
<linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<j-choudhary@ti.com>
Subject: [PATCH v2 4/5] arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node
Date: Fri, 14 Apr 2023 20:45:52 +0530 [thread overview]
Message-ID: <20230414151553.339599-5-j-choudhary@ti.com> (raw)
In-Reply-To: <20230414151553.339599-1-j-choudhary@ti.com>
From: Rahul T R <r-ravikumar@ti.com>
Add DSS and DP-bridge node for J784S4 SoC. DSS IP in J784S4 is
same as DSS IP in J721E, so same compatible is being used.
The DP is Cadence MHDP8546.
Signed-off-by: Rahul T R <r-ravikumar@ti.com>
[j-choudhary@ti.com: move all k3-j784s4-main.dtsi changes together]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
---
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 77 ++++++++++++++++++++++
1 file changed, 77 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 0cd692bc52e6..fc6071c16188 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -1373,4 +1373,81 @@ main_spi7: spi@2170000 {
clocks = <&k3_clks 383 1>;
status = "disabled";
};
+
+ mhdp: dp-bridge@a000000 {
+ compatible = "ti,j721e-mhdp8546";
+
+ reg = <0x0 0xa000000 0x0 0x30a00>,
+ <0x0 0x4f40000 0x0 0x20>;
+ reg-names = "mhdptx", "j721e-intg";
+
+ clocks = <&k3_clks 217 11>;
+
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
+
+ power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
+
+ status = "disabled";
+
+ dp0_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ dss: dss@4a00000 {
+ compatible = "ti,j721e-dss";
+ reg =
+ <0x00 0x04a00000 0x00 0x10000>,
+ <0x00 0x04a10000 0x00 0x10000>,
+ <0x00 0x04b00000 0x00 0x10000>,
+ <0x00 0x04b10000 0x00 0x10000>,
+
+ <0x00 0x04a20000 0x00 0x10000>,
+ <0x00 0x04a30000 0x00 0x10000>,
+ <0x00 0x04a50000 0x00 0x10000>,
+ <0x00 0x04a60000 0x00 0x10000>,
+
+ <0x00 0x04a70000 0x00 0x10000>,
+ <0x00 0x04a90000 0x00 0x10000>,
+ <0x00 0x04ab0000 0x00 0x10000>,
+ <0x00 0x04ad0000 0x00 0x10000>,
+
+ <0x00 0x04a80000 0x00 0x10000>,
+ <0x00 0x04aa0000 0x00 0x10000>,
+ <0x00 0x04ac0000 0x00 0x10000>,
+ <0x00 0x04ae0000 0x00 0x10000>,
+ <0x00 0x04af0000 0x00 0x10000>;
+
+ reg-names = "common_m", "common_s0",
+ "common_s1", "common_s2",
+ "vidl1", "vidl2","vid1","vid2",
+ "ovr1", "ovr2", "ovr3", "ovr4",
+ "vp1", "vp2", "vp3", "vp4",
+ "wb";
+
+ clocks = <&k3_clks 218 0>,
+ <&k3_clks 218 2>,
+ <&k3_clks 218 5>,
+ <&k3_clks 218 14>,
+ <&k3_clks 218 18>;
+ clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
+
+ power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
+
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common_m",
+ "common_s0",
+ "common_s1",
+ "common_s2";
+
+ status = "disabled";
+
+ dss_ports: ports {
+ };
+ };
};
--
2.25.1
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next prev parent reply other threads:[~2023-04-14 15:17 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-14 15:15 [PATCH v2 0/5] Add peripherals for J784S4 Jayesh Choudhary
2023-04-14 15:15 ` [PATCH v2 1/5] arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux Jayesh Choudhary
2023-04-17 4:37 ` Vignesh Raghavendra
2023-04-17 7:35 ` Jayesh Choudhary
2023-04-14 15:15 ` [PATCH v2 2/5] arm64: dts: ti: k3-j784s4: Add Main CPSW2G node Jayesh Choudhary
2023-04-14 15:15 ` [PATCH v2 3/5] arm64: dts: ti: k3-j784s4: Add WIZ and SERDES PHY nodes Jayesh Choudhary
2023-04-17 4:40 ` Vignesh Raghavendra
2023-04-17 7:36 ` Jayesh Choudhary
2023-04-14 15:15 ` Jayesh Choudhary [this message]
2023-04-14 15:15 ` [PATCH v2 5/5] arm64: dts: ti: k3-j784s4-evm: Enable DisplayPort-0 Jayesh Choudhary
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