From: Daniel Machon <daniel.machon@microchip.com>
To: <vkoul@kernel.org>
Cc: <kishon@kernel.org>, <Steen.Hegelund@microchip.com>,
<daniel.machon@microchip.com>, <UNGLinuxDriver@microchip.com>,
<joe@perches.com>, <linux-phy@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Subject: [PATCH 4/7] phy: sparx5-serdes: power down all CMUs by default
Date: Mon, 17 Apr 2023 20:03:32 +0200 [thread overview]
Message-ID: <20230417180335.2787494-5-daniel.machon@microchip.com> (raw)
In-Reply-To: <20230417180335.2787494-1-daniel.machon@microchip.com>
All CMUs are powered up initially. This uses needless power. This patch
makes sure all CMUs are powered down by default. This involves
configuring a number reference clock and power-down registers of the
CMU.
Individual CMUs are later powered up, when the serdes lanes are
configured.
Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
---
drivers/phy/microchip/sparx5_serdes.c | 51 +++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/drivers/phy/microchip/sparx5_serdes.c b/drivers/phy/microchip/sparx5_serdes.c
index d8620e0fae7b..0e9db7b36b60 100644
--- a/drivers/phy/microchip/sparx5_serdes.c
+++ b/drivers/phy/microchip/sparx5_serdes.c
@@ -1078,6 +1078,54 @@ static int sparx5_serdes_cmu_enable(struct sparx5_serdes_private *priv)
return err;
}
+static void sparx5_serdes_cmu_power_off(struct sparx5_serdes_private *priv)
+{
+ void __iomem *cmu_inst, *cmu_cfg_inst;
+ int i;
+
+ /* Power down each CMU */
+ for (i = 0; i < SPX5_CMU_MAX; i++) {
+ cmu_inst = sdx5_inst_get(priv, TARGET_SD_CMU, i);
+ cmu_cfg_inst = sdx5_inst_get(priv, TARGET_SD_CMU_CFG, i);
+
+ sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(0),
+ SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, cmu_cfg_inst,
+ SD_CMU_CFG_SD_CMU_CFG(0));
+
+ sdx5_inst_rmw(SD_CMU_CMU_05_CFG_REFCK_TERM_EN_SET(0),
+ SD_CMU_CMU_05_CFG_REFCK_TERM_EN, cmu_inst,
+ SD_CMU_CMU_05(0));
+
+ sdx5_inst_rmw(SD_CMU_CMU_09_CFG_EN_TX_CK_DN_SET(0),
+ SD_CMU_CMU_09_CFG_EN_TX_CK_DN, cmu_inst,
+ SD_CMU_CMU_09(0));
+
+ sdx5_inst_rmw(SD_CMU_CMU_06_CFG_VCO_PD_SET(1),
+ SD_CMU_CMU_06_CFG_VCO_PD, cmu_inst,
+ SD_CMU_CMU_06(0));
+
+ sdx5_inst_rmw(SD_CMU_CMU_09_CFG_EN_TX_CK_UP_SET(0),
+ SD_CMU_CMU_09_CFG_EN_TX_CK_UP, cmu_inst,
+ SD_CMU_CMU_09(0));
+
+ sdx5_inst_rmw(SD_CMU_CMU_08_CFG_CK_TREE_PD_SET(1),
+ SD_CMU_CMU_08_CFG_CK_TREE_PD, cmu_inst,
+ SD_CMU_CMU_08(0));
+
+ sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_REFCK_PD_SET(1) |
+ SD_CMU_CMU_0D_CFG_PD_DIV64_SET(1) |
+ SD_CMU_CMU_0D_CFG_PD_DIV66_SET(1),
+ SD_CMU_CMU_0D_CFG_REFCK_PD |
+ SD_CMU_CMU_0D_CFG_PD_DIV64 |
+ SD_CMU_CMU_0D_CFG_PD_DIV66, cmu_inst,
+ SD_CMU_CMU_0D(0));
+
+ sdx5_inst_rmw(SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD_SET(1),
+ SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD, cmu_inst,
+ SD_CMU_CMU_06(0));
+ }
+}
+
static void sparx5_sd25g28_reset(void __iomem *regs[],
struct sparx5_sd25g28_params *params,
u32 sd_index)
@@ -2521,6 +2569,9 @@ static int sparx5_serdes_probe(struct platform_device *pdev)
return err;
}
+ /* Power down all CMUs by default */
+ sparx5_serdes_cmu_power_off(priv);
+
provider = devm_of_phy_provider_register(priv->dev, sparx5_serdes_xlate);
return PTR_ERR_OR_ZERO(provider);
--
2.34.1
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next prev parent reply other threads:[~2023-04-17 18:04 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-17 18:03 [PATCH 0/7] Power down serdes lanes and CMUs initially Daniel Machon
2023-04-17 18:03 ` [PATCH 1/7] phy: sparx5-serdes: add registers required for SD/CMU power down Daniel Machon
2023-04-17 18:03 ` [PATCH 2/7] phy: sparx5-serdes: configure optimal quiet mode for serdes lanes Daniel Machon
2023-04-17 18:03 ` [PATCH 3/7] phy: sparx5-serdes: reorder CMU functions Daniel Machon
2023-04-17 18:03 ` Daniel Machon [this message]
2023-04-17 18:03 ` [PATCH 5/7] phy: sparx5-serdes: power on CMUs individually Daniel Machon
2023-04-17 18:03 ` [PATCH 6/7] phy: sparx5-serdes: remove power up of all CMUs Daniel Machon
2023-04-17 18:03 ` [PATCH 7/7] phy: sparx5-serdes: add skip_cmu_cfg check when configuring lanes Daniel Machon
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