[PATCH 0/4] riscv: Allow userspace to directly access perf counters

Alexandre Ghiti
2023-04-13T16:18:27Z

riscv used to allow direct access to cycle/time/instret counters,
bypassing the perf framework, this patchset intends to allow the user to
mmap any counter when accessed through perf. But we can't break the
existing behaviour so we introduce a sysctl perf_user_access like arm64
does, which defaults to the legacy mode described above.

The core of this patchset lies in patch 4, the first 3 patches are
simple fixes.

base-commit-tag: v6.3-rc1

Alexandre Ghiti (4):
perf: Fix wrong comment about default event_idx
include: riscv: Fix wrong include guard in riscv_pmu.h
riscv: Make legacy counter enum match the HW numbering
riscv: Enable perf counters user access only through perf

Documentation/admin-guide/sysctl/kernel.rst | 23 +++-
arch/riscv/include/asm/perf_event.h | 3 +
arch/riscv/kernel/Makefile | 2 +-
arch/riscv/kernel/perf_event.c | 65 +++++++++++
drivers/perf/riscv_pmu.c | 42 ++++++++
drivers/perf/riscv_pmu_legacy.c | 24 ++++-
drivers/perf/riscv_pmu_sbi.c | 113 ++++++++++++++++++--
include/linux/perf/riscv_pmu.h | 9 +-
include/linux/perf_event.h | 3 +-
tools/lib/perf/mmap.c | 65 +++++++++++
10 files changed, 332 insertions(+), 17 deletions(-)
create mode 100644 arch/riscv/kernel/perf_event.c

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2.37.2