* [PATCH v6 1/6] KVM: arm64: Move CPU ID feature registers emulation into a separate file
2023-04-04 3:53 [PATCH v6 0/6] Support writable CPU ID registers from userspace Jing Zhang
@ 2023-04-04 3:53 ` Jing Zhang
2023-04-04 3:53 ` [PATCH v6 2/6] KVM: arm64: Save ID registers' sanitized value per guest Jing Zhang
` (4 subsequent siblings)
5 siblings, 0 replies; 18+ messages in thread
From: Jing Zhang @ 2023-04-04 3:53 UTC (permalink / raw)
To: KVM, KVMARM, ARMLinux, Marc Zyngier, Oliver Upton
Cc: Will Deacon, Paolo Bonzini, James Morse, Alexandru Elisei,
Suzuki K Poulose, Fuad Tabba, Reiji Watanabe,
Raghavendra Rao Ananta, Jing Zhang
Create a new file id_regs.c for CPU ID feature registers emulation code,
which are moved from sys_regs.c and tweak sys_regs code accordingly.
No functional change intended.
Signed-off-by: Jing Zhang <jingzhangos@google.com>
---
arch/arm64/kvm/Makefile | 2 +-
arch/arm64/kvm/id_regs.c | 460 +++++++++++++++++++++++++++++++++++++
arch/arm64/kvm/sys_regs.c | 464 ++++----------------------------------
arch/arm64/kvm/sys_regs.h | 19 ++
4 files changed, 519 insertions(+), 426 deletions(-)
create mode 100644 arch/arm64/kvm/id_regs.c
diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile
index c0c050e53157..a6a315fcd81e 100644
--- a/arch/arm64/kvm/Makefile
+++ b/arch/arm64/kvm/Makefile
@@ -13,7 +13,7 @@ obj-$(CONFIG_KVM) += hyp/
kvm-y += arm.o mmu.o mmio.o psci.o hypercalls.o pvtime.o \
inject_fault.o va_layout.o handle_exit.o \
guest.o debug.o reset.o sys_regs.o stacktrace.o \
- vgic-sys-reg-v3.o fpsimd.o pkvm.o \
+ vgic-sys-reg-v3.o fpsimd.o pkvm.o id_regs.o \
arch_timer.o trng.o vmid.o emulate-nested.o nested.o \
vgic/vgic.o vgic/vgic-init.o \
vgic/vgic-irqfd.o vgic/vgic-v2.o \
diff --git a/arch/arm64/kvm/id_regs.c b/arch/arm64/kvm/id_regs.c
new file mode 100644
index 000000000000..96b4c43a5100
--- /dev/null
+++ b/arch/arm64/kvm/id_regs.c
@@ -0,0 +1,460 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023 - Google LLC
+ * Author: Jing Zhang <jingzhangos@google.com>
+ *
+ * Moved from arch/arm64/kvm/sys_regs.c
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bsearch.h>
+#include <linux/kvm_host.h>
+#include <asm/kvm_emulate.h>
+#include <asm/sysreg.h>
+#include <asm/cpufeature.h>
+#include <asm/kvm_nested.h>
+
+#include "sys_regs.h"
+
+static u8 vcpu_pmuver(const struct kvm_vcpu *vcpu)
+{
+ if (kvm_vcpu_has_pmu(vcpu))
+ return vcpu->kvm->arch.dfr0_pmuver.imp;
+
+ return vcpu->kvm->arch.dfr0_pmuver.unimp;
+}
+
+static u8 perfmon_to_pmuver(u8 perfmon)
+{
+ switch (perfmon) {
+ case ID_DFR0_EL1_PerfMon_PMUv3:
+ return ID_AA64DFR0_EL1_PMUVer_IMP;
+ case ID_DFR0_EL1_PerfMon_IMPDEF:
+ return ID_AA64DFR0_EL1_PMUVer_IMP_DEF;
+ default:
+ /* Anything ARMv8.1+ and NI have the same value. For now. */
+ return perfmon;
+ }
+}
+
+static u8 pmuver_to_perfmon(u8 pmuver)
+{
+ switch (pmuver) {
+ case ID_AA64DFR0_EL1_PMUVer_IMP:
+ return ID_DFR0_EL1_PerfMon_PMUv3;
+ case ID_AA64DFR0_EL1_PMUVer_IMP_DEF:
+ return ID_DFR0_EL1_PerfMon_IMPDEF;
+ default:
+ /* Anything ARMv8.1+ and NI have the same value. For now. */
+ return pmuver;
+ }
+}
+
+/* Read a sanitised cpufeature ID register by sys_reg_desc */
+static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r)
+{
+ u32 id = reg_to_encoding(r);
+ u64 val;
+
+ if (sysreg_visible_as_raz(vcpu, r))
+ return 0;
+
+ val = read_sanitised_ftr_reg(id);
+
+ switch (id) {
+ case SYS_ID_AA64PFR0_EL1:
+ if (!vcpu_has_sve(vcpu))
+ val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE);
+ val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU);
+ val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2);
+ val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2),
+ (u64)vcpu->kvm->arch.pfr0_csv2);
+ val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3);
+ val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3),
+ (u64)vcpu->kvm->arch.pfr0_csv3);
+ if (kvm_vgic_global_state.type == VGIC_V3) {
+ val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC);
+ val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC), 1);
+ }
+ break;
+ case SYS_ID_AA64PFR1_EL1:
+ if (!kvm_has_mte(vcpu->kvm))
+ val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE);
+
+ val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME);
+ break;
+ case SYS_ID_AA64ISAR1_EL1:
+ if (!vcpu_has_ptrauth(vcpu))
+ val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) |
+ ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) |
+ ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) |
+ ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI));
+ break;
+ case SYS_ID_AA64ISAR2_EL1:
+ if (!vcpu_has_ptrauth(vcpu))
+ val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) |
+ ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3));
+ if (!cpus_have_final_cap(ARM64_HAS_WFXT))
+ val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT);
+ break;
+ case SYS_ID_AA64DFR0_EL1:
+ /* Limit debug to ARMv8.0 */
+ val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer);
+ val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), 6);
+ /* Set PMUver to the required version */
+ val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
+ val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer),
+ vcpu_pmuver(vcpu));
+ /* Hide SPE from guests */
+ val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer);
+ break;
+ case SYS_ID_DFR0_EL1:
+ val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon);
+ val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon),
+ pmuver_to_perfmon(vcpu_pmuver(vcpu)));
+ break;
+ case SYS_ID_AA64MMFR2_EL1:
+ val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK;
+ break;
+ case SYS_ID_MMFR4_EL1:
+ val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX);
+ break;
+ }
+
+ return val;
+}
+
+/* cpufeature ID register access trap handlers */
+
+static bool access_id_reg(struct kvm_vcpu *vcpu,
+ struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ if (p->is_write)
+ return write_to_read_only(vcpu, p, r);
+
+ p->regval = read_id_reg(vcpu, r);
+ if (vcpu_has_nv(vcpu))
+ access_nested_id_reg(vcpu, p, r);
+
+ return true;
+}
+
+/*
+ * cpufeature ID register user accessors
+ *
+ * For now, these registers are immutable for userspace, so no values
+ * are stored, and for set_id_reg() we don't allow the effective value
+ * to be changed.
+ */
+static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
+ u64 *val)
+{
+ *val = read_id_reg(vcpu, rd);
+ return 0;
+}
+
+static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
+ u64 val)
+{
+ /* This is what we mean by invariant: you can't change it. */
+ if (val != read_id_reg(vcpu, rd))
+ return -EINVAL;
+
+ return 0;
+}
+
+static unsigned int id_visibility(const struct kvm_vcpu *vcpu,
+ const struct sys_reg_desc *r)
+{
+ u32 id = reg_to_encoding(r);
+
+ switch (id) {
+ case SYS_ID_AA64ZFR0_EL1:
+ if (!vcpu_has_sve(vcpu))
+ return REG_RAZ;
+ break;
+ }
+
+ return 0;
+}
+
+static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu,
+ const struct sys_reg_desc *r)
+{
+ /*
+ * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any
+ * EL. Promote to RAZ/WI in order to guarantee consistency between
+ * systems.
+ */
+ if (!kvm_supports_32bit_el0())
+ return REG_RAZ | REG_USER_WI;
+
+ return id_visibility(vcpu, r);
+}
+
+static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
+ const struct sys_reg_desc *rd,
+ u64 val)
+{
+ u8 csv2, csv3;
+
+ /*
+ * Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as
+ * it doesn't promise more than what is actually provided (the
+ * guest could otherwise be covered in ectoplasmic residue).
+ */
+ csv2 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_EL1_CSV2_SHIFT);
+ if (csv2 > 1 || (csv2 && arm64_get_spectre_v2_state() != SPECTRE_UNAFFECTED))
+ return -EINVAL;
+
+ /* Same thing for CSV3 */
+ csv3 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_EL1_CSV3_SHIFT);
+ if (csv3 > 1 || (csv3 && arm64_get_meltdown_state() != SPECTRE_UNAFFECTED))
+ return -EINVAL;
+
+ /* We can only differ with CSV[23], and anything else is an error */
+ val ^= read_id_reg(vcpu, rd);
+ val &= ~(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2) |
+ ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3));
+ if (val)
+ return -EINVAL;
+
+ vcpu->kvm->arch.pfr0_csv2 = csv2;
+ vcpu->kvm->arch.pfr0_csv3 = csv3;
+
+ return 0;
+}
+
+static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
+ const struct sys_reg_desc *rd,
+ u64 val)
+{
+ u8 pmuver, host_pmuver;
+ bool valid_pmu;
+
+ host_pmuver = kvm_arm_pmu_get_pmuver_limit();
+
+ /*
+ * Allow AA64DFR0_EL1.PMUver to be set from userspace as long
+ * as it doesn't promise more than what the HW gives us. We
+ * allow an IMPDEF PMU though, only if no PMU is supported
+ * (KVM backward compatibility handling).
+ */
+ pmuver = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), val);
+ if ((pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF && pmuver > host_pmuver))
+ return -EINVAL;
+
+ valid_pmu = (pmuver != 0 && pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF);
+
+ /* Make sure view register and PMU support do match */
+ if (kvm_vcpu_has_pmu(vcpu) != valid_pmu)
+ return -EINVAL;
+
+ /* We can only differ with PMUver, and anything else is an error */
+ val ^= read_id_reg(vcpu, rd);
+ val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
+ if (val)
+ return -EINVAL;
+
+ if (valid_pmu)
+ vcpu->kvm->arch.dfr0_pmuver.imp = pmuver;
+ else
+ vcpu->kvm->arch.dfr0_pmuver.unimp = pmuver;
+
+ return 0;
+}
+
+static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
+ const struct sys_reg_desc *rd,
+ u64 val)
+{
+ u8 perfmon, host_perfmon;
+ bool valid_pmu;
+
+ host_perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit());
+
+ /*
+ * Allow DFR0_EL1.PerfMon to be set from userspace as long as
+ * it doesn't promise more than what the HW gives us on the
+ * AArch64 side (as everything is emulated with that), and
+ * that this is a PMUv3.
+ */
+ perfmon = FIELD_GET(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), val);
+ if ((perfmon != ID_DFR0_EL1_PerfMon_IMPDEF && perfmon > host_perfmon) ||
+ (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3))
+ return -EINVAL;
+
+ valid_pmu = (perfmon != 0 && perfmon != ID_DFR0_EL1_PerfMon_IMPDEF);
+
+ /* Make sure view register and PMU support do match */
+ if (kvm_vcpu_has_pmu(vcpu) != valid_pmu)
+ return -EINVAL;
+
+ /* We can only differ with PerfMon, and anything else is an error */
+ val ^= read_id_reg(vcpu, rd);
+ val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon);
+ if (val)
+ return -EINVAL;
+
+ if (valid_pmu)
+ vcpu->kvm->arch.dfr0_pmuver.imp = perfmon_to_pmuver(perfmon);
+ else
+ vcpu->kvm->arch.dfr0_pmuver.unimp = perfmon_to_pmuver(perfmon);
+
+ return 0;
+}
+
+/* sys_reg_desc initialiser for known cpufeature ID registers */
+#define ID_SANITISED(name) { \
+ SYS_DESC(SYS_##name), \
+ .access = access_id_reg, \
+ .get_user = get_id_reg, \
+ .set_user = set_id_reg, \
+ .visibility = id_visibility, \
+}
+
+/* sys_reg_desc initialiser for known cpufeature ID registers */
+#define AA32_ID_SANITISED(name) { \
+ SYS_DESC(SYS_##name), \
+ .access = access_id_reg, \
+ .get_user = get_id_reg, \
+ .set_user = set_id_reg, \
+ .visibility = aa32_id_visibility, \
+}
+
+/*
+ * sys_reg_desc initialiser for architecturally unallocated cpufeature ID
+ * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
+ * (1 <= crm < 8, 0 <= Op2 < 8).
+ */
+#define ID_UNALLOCATED(crm, op2) { \
+ Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
+ .access = access_id_reg, \
+ .get_user = get_id_reg, \
+ .set_user = set_id_reg, \
+ .visibility = raz_visibility \
+}
+
+/*
+ * sys_reg_desc initialiser for known ID registers that we hide from guests.
+ * For now, these are exposed just like unallocated ID regs: they appear
+ * RAZ for the guest.
+ */
+#define ID_HIDDEN(name) { \
+ SYS_DESC(SYS_##name), \
+ .access = access_id_reg, \
+ .get_user = get_id_reg, \
+ .set_user = set_id_reg, \
+ .visibility = raz_visibility, \
+}
+
+const struct sys_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = {
+ /*
+ * ID regs: all ID_SANITISED() entries here must have corresponding
+ * entries in arm64_ftr_regs[].
+ */
+
+ /* AArch64 mappings of the AArch32 ID registers */
+ /* CRm=1 */
+ AA32_ID_SANITISED(ID_PFR0_EL1),
+ AA32_ID_SANITISED(ID_PFR1_EL1),
+ { SYS_DESC(SYS_ID_DFR0_EL1), .access = access_id_reg,
+ .get_user = get_id_reg, .set_user = set_id_dfr0_el1,
+ .visibility = aa32_id_visibility, },
+ ID_HIDDEN(ID_AFR0_EL1),
+ AA32_ID_SANITISED(ID_MMFR0_EL1),
+ AA32_ID_SANITISED(ID_MMFR1_EL1),
+ AA32_ID_SANITISED(ID_MMFR2_EL1),
+ AA32_ID_SANITISED(ID_MMFR3_EL1),
+
+ /* CRm=2 */
+ AA32_ID_SANITISED(ID_ISAR0_EL1),
+ AA32_ID_SANITISED(ID_ISAR1_EL1),
+ AA32_ID_SANITISED(ID_ISAR2_EL1),
+ AA32_ID_SANITISED(ID_ISAR3_EL1),
+ AA32_ID_SANITISED(ID_ISAR4_EL1),
+ AA32_ID_SANITISED(ID_ISAR5_EL1),
+ AA32_ID_SANITISED(ID_MMFR4_EL1),
+ AA32_ID_SANITISED(ID_ISAR6_EL1),
+
+ /* CRm=3 */
+ AA32_ID_SANITISED(MVFR0_EL1),
+ AA32_ID_SANITISED(MVFR1_EL1),
+ AA32_ID_SANITISED(MVFR2_EL1),
+ ID_UNALLOCATED(3, 3),
+ AA32_ID_SANITISED(ID_PFR2_EL1),
+ ID_HIDDEN(ID_DFR1_EL1),
+ AA32_ID_SANITISED(ID_MMFR5_EL1),
+ ID_UNALLOCATED(3, 7),
+
+ /* AArch64 ID registers */
+ /* CRm=4 */
+ { SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg,
+ .get_user = get_id_reg, .set_user = set_id_aa64pfr0_el1, },
+ ID_SANITISED(ID_AA64PFR1_EL1),
+ ID_UNALLOCATED(4, 2),
+ ID_UNALLOCATED(4, 3),
+ ID_SANITISED(ID_AA64ZFR0_EL1),
+ ID_HIDDEN(ID_AA64SMFR0_EL1),
+ ID_UNALLOCATED(4, 6),
+ ID_UNALLOCATED(4, 7),
+
+ /* CRm=5 */
+ { SYS_DESC(SYS_ID_AA64DFR0_EL1), .access = access_id_reg,
+ .get_user = get_id_reg, .set_user = set_id_aa64dfr0_el1, },
+ ID_SANITISED(ID_AA64DFR1_EL1),
+ ID_UNALLOCATED(5, 2),
+ ID_UNALLOCATED(5, 3),
+ ID_HIDDEN(ID_AA64AFR0_EL1),
+ ID_HIDDEN(ID_AA64AFR1_EL1),
+ ID_UNALLOCATED(5, 6),
+ ID_UNALLOCATED(5, 7),
+
+ /* CRm=6 */
+ ID_SANITISED(ID_AA64ISAR0_EL1),
+ ID_SANITISED(ID_AA64ISAR1_EL1),
+ ID_SANITISED(ID_AA64ISAR2_EL1),
+ ID_UNALLOCATED(6, 3),
+ ID_UNALLOCATED(6, 4),
+ ID_UNALLOCATED(6, 5),
+ ID_UNALLOCATED(6, 6),
+ ID_UNALLOCATED(6, 7),
+
+ /* CRm=7 */
+ ID_SANITISED(ID_AA64MMFR0_EL1),
+ ID_SANITISED(ID_AA64MMFR1_EL1),
+ ID_SANITISED(ID_AA64MMFR2_EL1),
+ ID_UNALLOCATED(7, 3),
+ ID_UNALLOCATED(7, 4),
+ ID_UNALLOCATED(7, 5),
+ ID_UNALLOCATED(7, 6),
+ ID_UNALLOCATED(7, 7),
+};
+
+/**
+ * emulate_id_reg - Emulate a guest access to an AArch64 CPU ID feature register
+ * @vcpu: The VCPU pointer
+ * @params: Decoded system register parameters
+ *
+ * Return: true if the ID register access was successful, false otherwise.
+ */
+int emulate_id_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params)
+{
+ const struct sys_reg_desc *r;
+
+ r = find_reg(params, id_reg_descs, ARRAY_SIZE(id_reg_descs));
+
+ if (likely(r)) {
+ perform_access(vcpu, params, r);
+ } else {
+ print_sys_reg_msg(params,
+ "Unsupported guest id_reg access at: %lx [%08lx]\n",
+ *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
+ kvm_inject_undefined(vcpu);
+ }
+
+ return 1;
+}
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 1b2c161120be..d16213adc07b 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -53,9 +53,9 @@ static bool read_from_write_only(struct kvm_vcpu *vcpu,
return false;
}
-static bool write_to_read_only(struct kvm_vcpu *vcpu,
- struct sys_reg_params *params,
- const struct sys_reg_desc *r)
+bool write_to_read_only(struct kvm_vcpu *vcpu,
+ struct sys_reg_params *params,
+ const struct sys_reg_desc *r)
{
WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n");
print_sys_reg_instr(params);
@@ -1169,163 +1169,11 @@ static bool access_arch_timer(struct kvm_vcpu *vcpu,
return true;
}
-static u8 vcpu_pmuver(const struct kvm_vcpu *vcpu)
-{
- if (kvm_vcpu_has_pmu(vcpu))
- return vcpu->kvm->arch.dfr0_pmuver.imp;
-
- return vcpu->kvm->arch.dfr0_pmuver.unimp;
-}
-
-static u8 perfmon_to_pmuver(u8 perfmon)
-{
- switch (perfmon) {
- case ID_DFR0_EL1_PerfMon_PMUv3:
- return ID_AA64DFR0_EL1_PMUVer_IMP;
- case ID_DFR0_EL1_PerfMon_IMPDEF:
- return ID_AA64DFR0_EL1_PMUVer_IMP_DEF;
- default:
- /* Anything ARMv8.1+ and NI have the same value. For now. */
- return perfmon;
- }
-}
-
-static u8 pmuver_to_perfmon(u8 pmuver)
-{
- switch (pmuver) {
- case ID_AA64DFR0_EL1_PMUVer_IMP:
- return ID_DFR0_EL1_PerfMon_PMUv3;
- case ID_AA64DFR0_EL1_PMUVer_IMP_DEF:
- return ID_DFR0_EL1_PerfMon_IMPDEF;
- default:
- /* Anything ARMv8.1+ and NI have the same value. For now. */
- return pmuver;
- }
-}
-
-/* Read a sanitised cpufeature ID register by sys_reg_desc */
-static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r)
-{
- u32 id = reg_to_encoding(r);
- u64 val;
-
- if (sysreg_visible_as_raz(vcpu, r))
- return 0;
-
- val = read_sanitised_ftr_reg(id);
-
- switch (id) {
- case SYS_ID_AA64PFR0_EL1:
- if (!vcpu_has_sve(vcpu))
- val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE);
- val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU);
- val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2);
- val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2);
- val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3);
- val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3);
- if (kvm_vgic_global_state.type == VGIC_V3) {
- val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC);
- val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC), 1);
- }
- break;
- case SYS_ID_AA64PFR1_EL1:
- if (!kvm_has_mte(vcpu->kvm))
- val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE);
-
- val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME);
- break;
- case SYS_ID_AA64ISAR1_EL1:
- if (!vcpu_has_ptrauth(vcpu))
- val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) |
- ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) |
- ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) |
- ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI));
- break;
- case SYS_ID_AA64ISAR2_EL1:
- if (!vcpu_has_ptrauth(vcpu))
- val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) |
- ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3));
- if (!cpus_have_final_cap(ARM64_HAS_WFXT))
- val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT);
- break;
- case SYS_ID_AA64DFR0_EL1:
- /* Limit debug to ARMv8.0 */
- val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer);
- val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), 6);
- /* Set PMUver to the required version */
- val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
- val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer),
- vcpu_pmuver(vcpu));
- /* Hide SPE from guests */
- val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer);
- break;
- case SYS_ID_DFR0_EL1:
- val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon);
- val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon),
- pmuver_to_perfmon(vcpu_pmuver(vcpu)));
- break;
- case SYS_ID_AA64MMFR2_EL1:
- val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK;
- break;
- case SYS_ID_MMFR4_EL1:
- val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX);
- break;
- }
-
- return val;
-}
-
-static unsigned int id_visibility(const struct kvm_vcpu *vcpu,
- const struct sys_reg_desc *r)
-{
- u32 id = reg_to_encoding(r);
-
- switch (id) {
- case SYS_ID_AA64ZFR0_EL1:
- if (!vcpu_has_sve(vcpu))
- return REG_RAZ;
- break;
- }
-
- return 0;
-}
-
-static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu,
- const struct sys_reg_desc *r)
-{
- /*
- * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any
- * EL. Promote to RAZ/WI in order to guarantee consistency between
- * systems.
- */
- if (!kvm_supports_32bit_el0())
- return REG_RAZ | REG_USER_WI;
-
- return id_visibility(vcpu, r);
-}
-
-static unsigned int raz_visibility(const struct kvm_vcpu *vcpu,
- const struct sys_reg_desc *r)
+unsigned int raz_visibility(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
{
return REG_RAZ;
}
-/* cpufeature ID register access trap handlers */
-
-static bool access_id_reg(struct kvm_vcpu *vcpu,
- struct sys_reg_params *p,
- const struct sys_reg_desc *r)
-{
- if (p->is_write)
- return write_to_read_only(vcpu, p, r);
-
- p->regval = read_id_reg(vcpu, r);
- if (vcpu_has_nv(vcpu))
- access_nested_id_reg(vcpu, p, r);
-
- return true;
-}
-
/* Visibility overrides for SVE-specific control registers */
static unsigned int sve_visibility(const struct kvm_vcpu *vcpu,
const struct sys_reg_desc *rd)
@@ -1336,144 +1184,6 @@ static unsigned int sve_visibility(const struct kvm_vcpu *vcpu,
return REG_HIDDEN;
}
-static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
- const struct sys_reg_desc *rd,
- u64 val)
-{
- u8 csv2, csv3;
-
- /*
- * Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as
- * it doesn't promise more than what is actually provided (the
- * guest could otherwise be covered in ectoplasmic residue).
- */
- csv2 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_EL1_CSV2_SHIFT);
- if (csv2 > 1 ||
- (csv2 && arm64_get_spectre_v2_state() != SPECTRE_UNAFFECTED))
- return -EINVAL;
-
- /* Same thing for CSV3 */
- csv3 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_EL1_CSV3_SHIFT);
- if (csv3 > 1 ||
- (csv3 && arm64_get_meltdown_state() != SPECTRE_UNAFFECTED))
- return -EINVAL;
-
- /* We can only differ with CSV[23], and anything else is an error */
- val ^= read_id_reg(vcpu, rd);
- val &= ~(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2) |
- ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3));
- if (val)
- return -EINVAL;
-
- vcpu->kvm->arch.pfr0_csv2 = csv2;
- vcpu->kvm->arch.pfr0_csv3 = csv3;
-
- return 0;
-}
-
-static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
- const struct sys_reg_desc *rd,
- u64 val)
-{
- u8 pmuver, host_pmuver;
- bool valid_pmu;
-
- host_pmuver = kvm_arm_pmu_get_pmuver_limit();
-
- /*
- * Allow AA64DFR0_EL1.PMUver to be set from userspace as long
- * as it doesn't promise more than what the HW gives us. We
- * allow an IMPDEF PMU though, only if no PMU is supported
- * (KVM backward compatibility handling).
- */
- pmuver = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), val);
- if ((pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF && pmuver > host_pmuver))
- return -EINVAL;
-
- valid_pmu = (pmuver != 0 && pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF);
-
- /* Make sure view register and PMU support do match */
- if (kvm_vcpu_has_pmu(vcpu) != valid_pmu)
- return -EINVAL;
-
- /* We can only differ with PMUver, and anything else is an error */
- val ^= read_id_reg(vcpu, rd);
- val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
- if (val)
- return -EINVAL;
-
- if (valid_pmu)
- vcpu->kvm->arch.dfr0_pmuver.imp = pmuver;
- else
- vcpu->kvm->arch.dfr0_pmuver.unimp = pmuver;
-
- return 0;
-}
-
-static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
- const struct sys_reg_desc *rd,
- u64 val)
-{
- u8 perfmon, host_perfmon;
- bool valid_pmu;
-
- host_perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit());
-
- /*
- * Allow DFR0_EL1.PerfMon to be set from userspace as long as
- * it doesn't promise more than what the HW gives us on the
- * AArch64 side (as everything is emulated with that), and
- * that this is a PMUv3.
- */
- perfmon = FIELD_GET(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), val);
- if ((perfmon != ID_DFR0_EL1_PerfMon_IMPDEF && perfmon > host_perfmon) ||
- (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3))
- return -EINVAL;
-
- valid_pmu = (perfmon != 0 && perfmon != ID_DFR0_EL1_PerfMon_IMPDEF);
-
- /* Make sure view register and PMU support do match */
- if (kvm_vcpu_has_pmu(vcpu) != valid_pmu)
- return -EINVAL;
-
- /* We can only differ with PerfMon, and anything else is an error */
- val ^= read_id_reg(vcpu, rd);
- val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon);
- if (val)
- return -EINVAL;
-
- if (valid_pmu)
- vcpu->kvm->arch.dfr0_pmuver.imp = perfmon_to_pmuver(perfmon);
- else
- vcpu->kvm->arch.dfr0_pmuver.unimp = perfmon_to_pmuver(perfmon);
-
- return 0;
-}
-
-/*
- * cpufeature ID register user accessors
- *
- * For now, these registers are immutable for userspace, so no values
- * are stored, and for set_id_reg() we don't allow the effective value
- * to be changed.
- */
-static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
- u64 *val)
-{
- *val = read_id_reg(vcpu, rd);
- return 0;
-}
-
-static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
- u64 val)
-{
- /* This is what we mean by invariant: you can't change it. */
- if (val != read_id_reg(vcpu, rd))
- return -EINVAL;
-
- return 0;
-}
-
static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
u64 *val)
{
@@ -1658,50 +1368,6 @@ static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu,
.visibility = elx2_visibility, \
}
-/* sys_reg_desc initialiser for known cpufeature ID registers */
-#define ID_SANITISED(name) { \
- SYS_DESC(SYS_##name), \
- .access = access_id_reg, \
- .get_user = get_id_reg, \
- .set_user = set_id_reg, \
- .visibility = id_visibility, \
-}
-
-/* sys_reg_desc initialiser for known cpufeature ID registers */
-#define AA32_ID_SANITISED(name) { \
- SYS_DESC(SYS_##name), \
- .access = access_id_reg, \
- .get_user = get_id_reg, \
- .set_user = set_id_reg, \
- .visibility = aa32_id_visibility, \
-}
-
-/*
- * sys_reg_desc initialiser for architecturally unallocated cpufeature ID
- * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
- * (1 <= crm < 8, 0 <= Op2 < 8).
- */
-#define ID_UNALLOCATED(crm, op2) { \
- Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
- .access = access_id_reg, \
- .get_user = get_id_reg, \
- .set_user = set_id_reg, \
- .visibility = raz_visibility \
-}
-
-/*
- * sys_reg_desc initialiser for known ID registers that we hide from guests.
- * For now, these are exposed just like unallocated ID regs: they appear
- * RAZ for the guest.
- */
-#define ID_HIDDEN(name) { \
- SYS_DESC(SYS_##name), \
- .access = access_id_reg, \
- .get_user = get_id_reg, \
- .set_user = set_id_reg, \
- .visibility = raz_visibility, \
-}
-
static bool access_sp_el1(struct kvm_vcpu *vcpu,
struct sys_reg_params *p,
const struct sys_reg_desc *r)
@@ -1738,6 +1404,8 @@ static bool access_spsr(struct kvm_vcpu *vcpu,
return true;
}
+extern const struct sys_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM];
+
/*
* Architected system registers.
* Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
@@ -1792,87 +1460,6 @@ static const struct sys_reg_desc sys_reg_descs[] = {
{ SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
- /*
- * ID regs: all ID_SANITISED() entries here must have corresponding
- * entries in arm64_ftr_regs[].
- */
-
- /* AArch64 mappings of the AArch32 ID registers */
- /* CRm=1 */
- AA32_ID_SANITISED(ID_PFR0_EL1),
- AA32_ID_SANITISED(ID_PFR1_EL1),
- { SYS_DESC(SYS_ID_DFR0_EL1), .access = access_id_reg,
- .get_user = get_id_reg, .set_user = set_id_dfr0_el1,
- .visibility = aa32_id_visibility, },
- ID_HIDDEN(ID_AFR0_EL1),
- AA32_ID_SANITISED(ID_MMFR0_EL1),
- AA32_ID_SANITISED(ID_MMFR1_EL1),
- AA32_ID_SANITISED(ID_MMFR2_EL1),
- AA32_ID_SANITISED(ID_MMFR3_EL1),
-
- /* CRm=2 */
- AA32_ID_SANITISED(ID_ISAR0_EL1),
- AA32_ID_SANITISED(ID_ISAR1_EL1),
- AA32_ID_SANITISED(ID_ISAR2_EL1),
- AA32_ID_SANITISED(ID_ISAR3_EL1),
- AA32_ID_SANITISED(ID_ISAR4_EL1),
- AA32_ID_SANITISED(ID_ISAR5_EL1),
- AA32_ID_SANITISED(ID_MMFR4_EL1),
- AA32_ID_SANITISED(ID_ISAR6_EL1),
-
- /* CRm=3 */
- AA32_ID_SANITISED(MVFR0_EL1),
- AA32_ID_SANITISED(MVFR1_EL1),
- AA32_ID_SANITISED(MVFR2_EL1),
- ID_UNALLOCATED(3,3),
- AA32_ID_SANITISED(ID_PFR2_EL1),
- ID_HIDDEN(ID_DFR1_EL1),
- AA32_ID_SANITISED(ID_MMFR5_EL1),
- ID_UNALLOCATED(3,7),
-
- /* AArch64 ID registers */
- /* CRm=4 */
- { SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg,
- .get_user = get_id_reg, .set_user = set_id_aa64pfr0_el1, },
- ID_SANITISED(ID_AA64PFR1_EL1),
- ID_UNALLOCATED(4,2),
- ID_UNALLOCATED(4,3),
- ID_SANITISED(ID_AA64ZFR0_EL1),
- ID_HIDDEN(ID_AA64SMFR0_EL1),
- ID_UNALLOCATED(4,6),
- ID_UNALLOCATED(4,7),
-
- /* CRm=5 */
- { SYS_DESC(SYS_ID_AA64DFR0_EL1), .access = access_id_reg,
- .get_user = get_id_reg, .set_user = set_id_aa64dfr0_el1, },
- ID_SANITISED(ID_AA64DFR1_EL1),
- ID_UNALLOCATED(5,2),
- ID_UNALLOCATED(5,3),
- ID_HIDDEN(ID_AA64AFR0_EL1),
- ID_HIDDEN(ID_AA64AFR1_EL1),
- ID_UNALLOCATED(5,6),
- ID_UNALLOCATED(5,7),
-
- /* CRm=6 */
- ID_SANITISED(ID_AA64ISAR0_EL1),
- ID_SANITISED(ID_AA64ISAR1_EL1),
- ID_SANITISED(ID_AA64ISAR2_EL1),
- ID_UNALLOCATED(6,3),
- ID_UNALLOCATED(6,4),
- ID_UNALLOCATED(6,5),
- ID_UNALLOCATED(6,6),
- ID_UNALLOCATED(6,7),
-
- /* CRm=7 */
- ID_SANITISED(ID_AA64MMFR0_EL1),
- ID_SANITISED(ID_AA64MMFR1_EL1),
- ID_SANITISED(ID_AA64MMFR2_EL1),
- ID_UNALLOCATED(7,3),
- ID_UNALLOCATED(7,4),
- ID_UNALLOCATED(7,5),
- ID_UNALLOCATED(7,6),
- ID_UNALLOCATED(7,7),
-
{ SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
{ SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 },
{ SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
@@ -2574,7 +2161,7 @@ int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu)
return 1;
}
-static void perform_access(struct kvm_vcpu *vcpu,
+void perform_access(struct kvm_vcpu *vcpu,
struct sys_reg_params *params,
const struct sys_reg_desc *r)
{
@@ -2949,6 +2536,9 @@ int kvm_handle_sys_reg(struct kvm_vcpu *vcpu)
params = esr_sys64_to_params(esr);
params.regval = vcpu_get_reg(vcpu, Rt);
+ if (is_id_reg(reg_to_encoding(¶ms)))
+ return emulate_id_reg(vcpu, ¶ms);
+
if (!emulate_sys_reg(vcpu, ¶ms))
return 1;
@@ -3168,6 +2758,7 @@ int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg,
int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
{
void __user *uaddr = (void __user *)(unsigned long)reg->addr;
+ struct sys_reg_params params;
int err;
if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
@@ -3177,6 +2768,13 @@ int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg
if (err != -ENOENT)
return err;
+ if (!index_to_params(reg->id, ¶ms))
+ return -ENOENT;
+
+ if (is_id_reg(reg_to_encoding(¶ms)))
+ return kvm_sys_reg_get_user(vcpu, reg,
+ id_reg_descs, ARRAY_SIZE(id_reg_descs));
+
return kvm_sys_reg_get_user(vcpu, reg,
sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
}
@@ -3212,6 +2810,7 @@ int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg,
int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
{
void __user *uaddr = (void __user *)(unsigned long)reg->addr;
+ struct sys_reg_params params;
int err;
if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
@@ -3221,6 +2820,13 @@ int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg
if (err != -ENOENT)
return err;
+ if (!index_to_params(reg->id, ¶ms))
+ return -ENOENT;
+
+ if (is_id_reg(reg_to_encoding(¶ms)))
+ return kvm_sys_reg_set_user(vcpu, reg,
+ id_reg_descs, ARRAY_SIZE(id_reg_descs));
+
return kvm_sys_reg_set_user(vcpu, reg,
sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
}
@@ -3290,14 +2896,15 @@ static int walk_one_sys_reg(const struct kvm_vcpu *vcpu,
}
/* Assumed ordered tables, see kvm_sys_reg_table_init. */
-static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
+static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind,
+ const struct sys_reg_desc table[], unsigned int num)
{
const struct sys_reg_desc *i2, *end2;
unsigned int total = 0;
int err;
- i2 = sys_reg_descs;
- end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
+ i2 = table;
+ end2 = table + num;
while (i2 != end2) {
err = walk_one_sys_reg(vcpu, i2++, &uind, &total);
@@ -3311,7 +2918,8 @@ unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
{
return ARRAY_SIZE(invariant_sys_regs)
+ num_demux_regs()
- + walk_sys_regs(vcpu, (u64 __user *)NULL);
+ + walk_sys_regs(vcpu, (u64 __user *)NULL, id_reg_descs, ARRAY_SIZE(id_reg_descs))
+ + walk_sys_regs(vcpu, (u64 __user *)NULL, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
}
int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
@@ -3326,7 +2934,12 @@ int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
uindices++;
}
- err = walk_sys_regs(vcpu, uindices);
+ err = walk_sys_regs(vcpu, uindices, id_reg_descs, ARRAY_SIZE(id_reg_descs));
+ if (err < 0)
+ return err;
+ uindices += err;
+
+ err = walk_sys_regs(vcpu, uindices, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
if (err < 0)
return err;
uindices += err;
@@ -3340,6 +2953,7 @@ int __init kvm_sys_reg_table_init(void)
unsigned int i;
/* Make sure tables are unique and in order. */
+ valid &= check_sysreg_table(id_reg_descs, ARRAY_SIZE(id_reg_descs), false);
valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false);
valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true);
valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true);
diff --git a/arch/arm64/kvm/sys_regs.h b/arch/arm64/kvm/sys_regs.h
index 6b11f2cc7146..7ce546a8be60 100644
--- a/arch/arm64/kvm/sys_regs.h
+++ b/arch/arm64/kvm/sys_regs.h
@@ -210,6 +210,19 @@ find_reg(const struct sys_reg_params *params, const struct sys_reg_desc table[],
return __inline_bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
}
+/*
+ * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is
+ * (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8.
+ */
+static inline bool is_id_reg(u32 id)
+{
+ return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 &&
+ sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 &&
+ sys_reg_CRm(id) < 8);
+}
+
+void perform_access(struct kvm_vcpu *vcpu, struct sys_reg_params *params,
+ const struct sys_reg_desc *r);
const struct sys_reg_desc *get_reg_by_id(u64 id,
const struct sys_reg_desc table[],
unsigned int num);
@@ -220,6 +233,10 @@ int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg,
const struct sys_reg_desc table[], unsigned int num);
int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg,
const struct sys_reg_desc table[], unsigned int num);
+bool write_to_read_only(struct kvm_vcpu *vcpu,
+ struct sys_reg_params *params, const struct sys_reg_desc *r);
+unsigned int raz_visibility(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r);
+int emulate_id_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params);
#define AA32(_x) .aarch32_map = AA32_##_x
#define Op0(_x) .Op0 = _x
@@ -234,4 +251,6 @@ int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg,
CRn(sys_reg_CRn(reg)), CRm(sys_reg_CRm(reg)), \
Op2(sys_reg_Op2(reg))
+#define KVM_ARM_ID_REG_NUM 56
+
#endif /* __ARM64_KVM_SYS_REGS_LOCAL_H__ */
--
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^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v6 2/6] KVM: arm64: Save ID registers' sanitized value per guest
2023-04-04 3:53 [PATCH v6 0/6] Support writable CPU ID registers from userspace Jing Zhang
2023-04-04 3:53 ` [PATCH v6 1/6] KVM: arm64: Move CPU ID feature registers emulation into a separate file Jing Zhang
@ 2023-04-04 3:53 ` Jing Zhang
2023-04-04 3:53 ` [PATCH v6 3/6] KVM: arm64: Use per guest ID register for ID_AA64PFR0_EL1.[CSV2|CSV3] Jing Zhang
` (3 subsequent siblings)
5 siblings, 0 replies; 18+ messages in thread
From: Jing Zhang @ 2023-04-04 3:53 UTC (permalink / raw)
To: KVM, KVMARM, ARMLinux, Marc Zyngier, Oliver Upton
Cc: Will Deacon, Paolo Bonzini, James Morse, Alexandru Elisei,
Suzuki K Poulose, Fuad Tabba, Reiji Watanabe,
Raghavendra Rao Ananta, Jing Zhang
Introduce id_regs[] in kvm_arch as a storage of guest's ID registers,
and save ID registers' sanitized value in the array at KVM_CREATE_VM.
Use the saved ones when ID registers are read by the guest or
userspace (via KVM_GET_ONE_REG).
No functional change intended.
Co-developed-by: Reiji Watanabe <reijiw@google.com>
Signed-off-by: Reiji Watanabe <reijiw@google.com>
Signed-off-by: Jing Zhang <jingzhangos@google.com>
---
arch/arm64/include/asm/kvm_host.h | 21 +++++++++++++
arch/arm64/kvm/arm.c | 1 +
arch/arm64/kvm/id_regs.c | 49 +++++++++++++++++++++++++------
arch/arm64/kvm/sys_regs.c | 2 +-
arch/arm64/kvm/sys_regs.h | 3 +-
5 files changed, 64 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index bcd774d74f34..f0588bdce0ef 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -177,6 +177,22 @@ struct kvm_smccc_features {
unsigned long vendor_hyp_bmap;
};
+/*
+ * Emualted CPU ID registers per VM
+ * (Op0, Op1, CRn, CRm, Op2) of the ID registers to be saved in it
+ * is (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8.
+ *
+ * These emulated idregs are VM-wide, but accessed from the context of a vCPU.
+ * Updating multiple id regs with dependencies needs to be guarded by
+ * kvm_arch.config_lock.
+ */
+#define KVM_ARM_ID_REG_NUM 56
+#define IDREG_IDX(id) (((sys_reg_CRm(id) - 1) << 3) | sys_reg_Op2(id))
+#define IDREG(kvm, id) kvm->arch.idregs.regs[IDREG_IDX(id)]
+struct kvm_idregs {
+ u64 regs[KVM_ARM_ID_REG_NUM];
+};
+
typedef unsigned int pkvm_handle_t;
struct kvm_protected_vm {
@@ -243,6 +259,9 @@ struct kvm_arch {
/* Hypercall features firmware registers' descriptor */
struct kvm_smccc_features smccc_feat;
+ /* Emulated CPU ID registers */
+ struct kvm_idregs idregs;
+
/*
* For an untrusted host VM, 'pkvm.handle' is used to lookup
* the associated pKVM instance in the hypervisor.
@@ -1008,6 +1027,8 @@ int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
long kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm,
struct kvm_arm_copy_mte_tags *copy_tags);
+void kvm_arm_init_id_regs(struct kvm *kvm);
+
/* Guest/host FPSIMD coordination helpers */
int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu);
void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu);
diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index 3bd732eaf087..1bf6030c8946 100644
--- a/arch/arm64/kvm/arm.c
+++ b/arch/arm64/kvm/arm.c
@@ -153,6 +153,7 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
set_default_spectre(kvm);
kvm_arm_init_hypercalls(kvm);
+ kvm_arm_init_id_regs(kvm);
/*
* Initialise the default PMUver before there is a chance to
diff --git a/arch/arm64/kvm/id_regs.c b/arch/arm64/kvm/id_regs.c
index 96b4c43a5100..7e78957085fc 100644
--- a/arch/arm64/kvm/id_regs.c
+++ b/arch/arm64/kvm/id_regs.c
@@ -52,16 +52,9 @@ static u8 pmuver_to_perfmon(u8 pmuver)
}
}
-/* Read a sanitised cpufeature ID register by sys_reg_desc */
-static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r)
+u64 kvm_arm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id)
{
- u32 id = reg_to_encoding(r);
- u64 val;
-
- if (sysreg_visible_as_raz(vcpu, r))
- return 0;
-
- val = read_sanitised_ftr_reg(id);
+ u64 val = IDREG(vcpu->kvm, id);
switch (id) {
case SYS_ID_AA64PFR0_EL1:
@@ -126,6 +119,14 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r
return val;
}
+static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r)
+{
+ if (sysreg_visible_as_raz(vcpu, r))
+ return 0;
+
+ return kvm_arm_read_id_reg(vcpu, reg_to_encoding(r));
+}
+
/* cpufeature ID register access trap handlers */
static bool access_id_reg(struct kvm_vcpu *vcpu,
@@ -458,3 +459,33 @@ int emulate_id_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params)
return 1;
}
+
+/*
+ * Set the guest's ID registers that are defined in id_reg_descs[]
+ * with ID_SANITISED() to the host's sanitized value.
+ */
+void kvm_arm_init_id_regs(struct kvm *kvm)
+{
+ int i;
+ u32 id;
+ u64 val;
+
+ for (i = 0; i < ARRAY_SIZE(id_reg_descs); i++) {
+ id = reg_to_encoding(&id_reg_descs[i]);
+ if (WARN_ON_ONCE(!is_id_reg(id)))
+ /* Shouldn't happen */
+ continue;
+
+ /*
+ * Some hidden ID registers which are not in arm64_ftr_regs[]
+ * would cause warnings from read_sanitised_ftr_reg().
+ * Skip those ID registers to avoid the warnings.
+ */
+ if (id_reg_descs[i].visibility == raz_visibility)
+ /* Hidden or reserved ID register */
+ continue;
+
+ val = read_sanitised_ftr_reg(id);
+ IDREG(kvm, id) = val;
+ }
+}
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index d16213adc07b..15979c2b87ab 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -364,7 +364,7 @@ static bool trap_loregion(struct kvm_vcpu *vcpu,
struct sys_reg_params *p,
const struct sys_reg_desc *r)
{
- u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
+ u64 val = kvm_arm_read_id_reg(vcpu, SYS_ID_AA64MMFR1_EL1);
u32 sr = reg_to_encoding(r);
if (!(val & (0xfUL << ID_AA64MMFR1_EL1_LO_SHIFT))) {
diff --git a/arch/arm64/kvm/sys_regs.h b/arch/arm64/kvm/sys_regs.h
index 7ce546a8be60..e88fd77309b2 100644
--- a/arch/arm64/kvm/sys_regs.h
+++ b/arch/arm64/kvm/sys_regs.h
@@ -237,6 +237,7 @@ bool write_to_read_only(struct kvm_vcpu *vcpu,
struct sys_reg_params *params, const struct sys_reg_desc *r);
unsigned int raz_visibility(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r);
int emulate_id_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params);
+u64 kvm_arm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id);
#define AA32(_x) .aarch32_map = AA32_##_x
#define Op0(_x) .Op0 = _x
@@ -251,6 +252,4 @@ int emulate_id_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params);
CRn(sys_reg_CRn(reg)), CRm(sys_reg_CRm(reg)), \
Op2(sys_reg_Op2(reg))
-#define KVM_ARM_ID_REG_NUM 56
-
#endif /* __ARM64_KVM_SYS_REGS_LOCAL_H__ */
--
2.40.0.348.gf938b09366-goog
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^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v6 3/6] KVM: arm64: Use per guest ID register for ID_AA64PFR0_EL1.[CSV2|CSV3]
2023-04-04 3:53 [PATCH v6 0/6] Support writable CPU ID registers from userspace Jing Zhang
2023-04-04 3:53 ` [PATCH v6 1/6] KVM: arm64: Move CPU ID feature registers emulation into a separate file Jing Zhang
2023-04-04 3:53 ` [PATCH v6 2/6] KVM: arm64: Save ID registers' sanitized value per guest Jing Zhang
@ 2023-04-04 3:53 ` Jing Zhang
2023-04-04 3:53 ` [PATCH v6 4/6] KVM: arm64: Use per guest ID register for ID_AA64DFR0_EL1.PMUVer Jing Zhang
` (2 subsequent siblings)
5 siblings, 0 replies; 18+ messages in thread
From: Jing Zhang @ 2023-04-04 3:53 UTC (permalink / raw)
To: KVM, KVMARM, ARMLinux, Marc Zyngier, Oliver Upton
Cc: Will Deacon, Paolo Bonzini, James Morse, Alexandru Elisei,
Suzuki K Poulose, Fuad Tabba, Reiji Watanabe,
Raghavendra Rao Ananta, Jing Zhang
With per guest ID registers, ID_AA64PFR0_EL1.[CSV2|CSV3] settings from
userspace can be stored in its corresponding ID register.
The setting of CSV bits for protected VMs are removed according to the
discussion from Fuad below:
https://lore.kernel.org/all/CA+EHjTwXA9TprX4jeG+-D+c8v9XG+oFdU1o6TSkvVye145_OvA@mail.gmail.com
Besides the removal of CSV bits setting for protected VMs, No other
functional change intended.
Signed-off-by: Jing Zhang <jingzhangos@google.com>
---
arch/arm64/include/asm/kvm_host.h | 2 --
arch/arm64/kvm/arm.c | 17 ----------------
arch/arm64/kvm/hyp/nvhe/sys_regs.c | 7 -------
arch/arm64/kvm/id_regs.c | 31 ++++++++++++++++++++++--------
4 files changed, 23 insertions(+), 34 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index f0588bdce0ef..67a55177fd83 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -249,8 +249,6 @@ struct kvm_arch {
cpumask_var_t supported_cpus;
- u8 pfr0_csv2;
- u8 pfr0_csv3;
struct {
u8 imp:4;
u8 unimp:4;
diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index 1bf6030c8946..64e1c19e5a9b 100644
--- a/arch/arm64/kvm/arm.c
+++ b/arch/arm64/kvm/arm.c
@@ -104,22 +104,6 @@ static int kvm_arm_default_max_vcpus(void)
return vgic_present ? kvm_vgic_get_max_vcpus() : KVM_MAX_VCPUS;
}
-static void set_default_spectre(struct kvm *kvm)
-{
- /*
- * The default is to expose CSV2 == 1 if the HW isn't affected.
- * Although this is a per-CPU feature, we make it global because
- * asymmetric systems are just a nuisance.
- *
- * Userspace can override this as long as it doesn't promise
- * the impossible.
- */
- if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED)
- kvm->arch.pfr0_csv2 = 1;
- if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED)
- kvm->arch.pfr0_csv3 = 1;
-}
-
/**
* kvm_arch_init_vm - initializes a VM data structure
* @kvm: pointer to the KVM struct
@@ -151,7 +135,6 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
/* The maximum number of VCPUs is limited by the host's GIC model */
kvm->max_vcpus = kvm_arm_default_max_vcpus();
- set_default_spectre(kvm);
kvm_arm_init_hypercalls(kvm);
kvm_arm_init_id_regs(kvm);
diff --git a/arch/arm64/kvm/hyp/nvhe/sys_regs.c b/arch/arm64/kvm/hyp/nvhe/sys_regs.c
index 08d2b004f4b7..edd969a1f36b 100644
--- a/arch/arm64/kvm/hyp/nvhe/sys_regs.c
+++ b/arch/arm64/kvm/hyp/nvhe/sys_regs.c
@@ -85,19 +85,12 @@ static u64 get_restricted_features_unsigned(u64 sys_reg_val,
static u64 get_pvm_id_aa64pfr0(const struct kvm_vcpu *vcpu)
{
- const struct kvm *kvm = (const struct kvm *)kern_hyp_va(vcpu->kvm);
u64 set_mask = 0;
u64 allow_mask = PVM_ID_AA64PFR0_ALLOW;
set_mask |= get_restricted_features_unsigned(id_aa64pfr0_el1_sys_val,
PVM_ID_AA64PFR0_RESTRICT_UNSIGNED);
- /* Spectre and Meltdown mitigation in KVM */
- set_mask |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2),
- (u64)kvm->arch.pfr0_csv2);
- set_mask |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3),
- (u64)kvm->arch.pfr0_csv3);
-
return (id_aa64pfr0_el1_sys_val & allow_mask) | set_mask;
}
diff --git a/arch/arm64/kvm/id_regs.c b/arch/arm64/kvm/id_regs.c
index 7e78957085fc..291311b1ecca 100644
--- a/arch/arm64/kvm/id_regs.c
+++ b/arch/arm64/kvm/id_regs.c
@@ -61,12 +61,6 @@ u64 kvm_arm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id)
if (!vcpu_has_sve(vcpu))
val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE);
val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU);
- val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2);
- val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2),
- (u64)vcpu->kvm->arch.pfr0_csv2);
- val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3);
- val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3),
- (u64)vcpu->kvm->arch.pfr0_csv3);
if (kvm_vgic_global_state.type == VGIC_V3) {
val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC);
val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC), 1);
@@ -201,6 +195,7 @@ static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
u64 val)
{
u8 csv2, csv3;
+ u64 sval = val;
/*
* Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as
@@ -223,8 +218,7 @@ static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
if (val)
return -EINVAL;
- vcpu->kvm->arch.pfr0_csv2 = csv2;
- vcpu->kvm->arch.pfr0_csv3 = csv3;
+ IDREG(vcpu->kvm, reg_to_encoding(rd)) = sval;
return 0;
}
@@ -488,4 +482,25 @@ void kvm_arm_init_id_regs(struct kvm *kvm)
val = read_sanitised_ftr_reg(id);
IDREG(kvm, id) = val;
}
+
+ /*
+ * The default is to expose CSV2 == 1 if the HW isn't affected.
+ * Although this is a per-CPU feature, we make it global because
+ * asymmetric systems are just a nuisance.
+ *
+ * Userspace can override this as long as it doesn't promise
+ * the impossible.
+ */
+ val = IDREG(kvm, SYS_ID_AA64PFR0_EL1);
+
+ if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) {
+ val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2);
+ val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2), 1);
+ }
+ if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) {
+ val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3);
+ val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3), 1);
+ }
+
+ IDREG(kvm, SYS_ID_AA64PFR0_EL1) = val;
}
--
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^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v6 4/6] KVM: arm64: Use per guest ID register for ID_AA64DFR0_EL1.PMUVer
2023-04-04 3:53 [PATCH v6 0/6] Support writable CPU ID registers from userspace Jing Zhang
` (2 preceding siblings ...)
2023-04-04 3:53 ` [PATCH v6 3/6] KVM: arm64: Use per guest ID register for ID_AA64PFR0_EL1.[CSV2|CSV3] Jing Zhang
@ 2023-04-04 3:53 ` Jing Zhang
2023-04-04 16:59 ` kernel test robot
` (2 more replies)
2023-04-04 3:53 ` [PATCH v6 5/6] KVM: arm64: Reuse fields of sys_reg_desc for idreg Jing Zhang
2023-04-04 3:53 ` [PATCH v6 6/6] KVM: arm64: Refactor writings for PMUVer/CSV2/CSV3 Jing Zhang
5 siblings, 3 replies; 18+ messages in thread
From: Jing Zhang @ 2023-04-04 3:53 UTC (permalink / raw)
To: KVM, KVMARM, ARMLinux, Marc Zyngier, Oliver Upton
Cc: Will Deacon, Paolo Bonzini, James Morse, Alexandru Elisei,
Suzuki K Poulose, Fuad Tabba, Reiji Watanabe,
Raghavendra Rao Ananta, Jing Zhang
With per guest ID registers, PMUver settings from userspace
can be stored in its corresponding ID register.
No functional change intended.
Signed-off-by: Jing Zhang <jingzhangos@google.com>
---
arch/arm64/include/asm/kvm_host.h | 11 +++----
arch/arm64/kvm/arm.c | 6 ----
arch/arm64/kvm/id_regs.c | 50 ++++++++++++++++++++++++-------
include/kvm/arm_pmu.h | 5 ++--
4 files changed, 49 insertions(+), 23 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 67a55177fd83..da46a2729581 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -237,6 +237,12 @@ struct kvm_arch {
#define KVM_ARCH_FLAG_EL1_32BIT 4
/* PSCI SYSTEM_SUSPEND enabled for the guest */
#define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 5
+ /*
+ * AA64DFR0_EL1.PMUver was set as ID_AA64DFR0_EL1_PMUVer_IMP_DEF
+ * or DFR0_EL1.PerfMon was set as ID_DFR0_EL1_PerfMon_IMPDEF from
+ * userspace for VCPUs without PMU.
+ */
+#define KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU 6
unsigned long flags;
@@ -249,11 +255,6 @@ struct kvm_arch {
cpumask_var_t supported_cpus;
- struct {
- u8 imp:4;
- u8 unimp:4;
- } dfr0_pmuver;
-
/* Hypercall features firmware registers' descriptor */
struct kvm_smccc_features smccc_feat;
diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index 64e1c19e5a9b..3fe28d545b54 100644
--- a/arch/arm64/kvm/arm.c
+++ b/arch/arm64/kvm/arm.c
@@ -138,12 +138,6 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
kvm_arm_init_hypercalls(kvm);
kvm_arm_init_id_regs(kvm);
- /*
- * Initialise the default PMUver before there is a chance to
- * create an actual PMU.
- */
- kvm->arch.dfr0_pmuver.imp = kvm_arm_pmu_get_pmuver_limit();
-
return 0;
err_free_cpumask:
diff --git a/arch/arm64/kvm/id_regs.c b/arch/arm64/kvm/id_regs.c
index 291311b1ecca..6f65d30693fe 100644
--- a/arch/arm64/kvm/id_regs.c
+++ b/arch/arm64/kvm/id_regs.c
@@ -21,9 +21,12 @@
static u8 vcpu_pmuver(const struct kvm_vcpu *vcpu)
{
if (kvm_vcpu_has_pmu(vcpu))
- return vcpu->kvm->arch.dfr0_pmuver.imp;
+ return FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer),
+ IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1));
+ else if (test_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags))
+ return ID_AA64DFR0_EL1_PMUVer_IMP_DEF;
- return vcpu->kvm->arch.dfr0_pmuver.unimp;
+ return 0;
}
static u8 perfmon_to_pmuver(u8 perfmon)
@@ -254,10 +257,20 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
if (val)
return -EINVAL;
- if (valid_pmu)
- vcpu->kvm->arch.dfr0_pmuver.imp = pmuver;
- else
- vcpu->kvm->arch.dfr0_pmuver.unimp = pmuver;
+ if (valid_pmu) {
+ mutex_lock(&vcpu->kvm->arch.config_lock);
+ IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
+ IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK,
+ pmuver);
+
+ IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &= ~ID_DFR0_EL1_PerfMon_MASK;
+ IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK,
+ pmuver_to_perfmon(pmuver));
+ mutex_unlock(&vcpu->kvm->arch.config_lock);
+ } else {
+ assign_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags,
+ pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF);
+ }
return 0;
}
@@ -294,10 +307,19 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
if (val)
return -EINVAL;
- if (valid_pmu)
- vcpu->kvm->arch.dfr0_pmuver.imp = perfmon_to_pmuver(perfmon);
- else
- vcpu->kvm->arch.dfr0_pmuver.unimp = perfmon_to_pmuver(perfmon);
+ if (valid_pmu) {
+ mutex_lock(&vcpu->kvm->arch.config_lock);
+ IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &= ~ID_DFR0_EL1_PerfMon_MASK;
+ IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK, perfmon);
+
+ IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
+ IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK,
+ perfmon_to_pmuver(perfmon));
+ mutex_unlock(&vcpu->kvm->arch.config_lock);
+ } else {
+ assign_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags,
+ perfmon == ID_DFR0_EL1_PerfMon_IMPDEF);
+ }
return 0;
}
@@ -503,4 +525,12 @@ void kvm_arm_init_id_regs(struct kvm *kvm)
}
IDREG(kvm, SYS_ID_AA64PFR0_EL1) = val;
+
+ /*
+ * Initialise the default PMUver before there is a chance to
+ * create an actual PMU.
+ */
+ IDREG(kvm, SYS_ID_AA64DFR0_EL1) &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
+ IDREG(kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer),
+ kvm_arm_pmu_get_pmuver_limit());
}
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 628775334d5e..856ac59b6821 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -92,8 +92,9 @@ void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu);
/*
* Evaluates as true when emulating PMUv3p5, and false otherwise.
*/
-#define kvm_pmu_is_3p5(vcpu) \
- (vcpu->kvm->arch.dfr0_pmuver.imp >= ID_AA64DFR0_EL1_PMUVer_V3P5)
+#define kvm_pmu_is_3p5(vcpu) \
+ (FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), \
+ IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1)) >= ID_AA64DFR0_EL1_PMUVer_V3P5)
u8 kvm_arm_pmu_get_pmuver_limit(void);
--
2.40.0.348.gf938b09366-goog
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v6 4/6] KVM: arm64: Use per guest ID register for ID_AA64DFR0_EL1.PMUVer
2023-04-04 3:53 ` [PATCH v6 4/6] KVM: arm64: Use per guest ID register for ID_AA64DFR0_EL1.PMUVer Jing Zhang
@ 2023-04-04 16:59 ` kernel test robot
2023-04-11 6:47 ` kernel test robot
2023-04-19 3:40 ` Reiji Watanabe
2 siblings, 0 replies; 18+ messages in thread
From: kernel test robot @ 2023-04-04 16:59 UTC (permalink / raw)
To: Jing Zhang, KVM, KVMARM, ARMLinux, Marc Zyngier, Oliver Upton
Cc: oe-kbuild-all, Will Deacon, Paolo Bonzini, James Morse,
Alexandru Elisei, Suzuki K Poulose, Fuad Tabba, Reiji Watanabe,
Raghavendra Rao Ananta, Jing Zhang
Hi Jing,
kernel test robot noticed the following build errors:
[auto build test ERROR on 7e364e56293bb98cae1b55fd835f5991c4e96e7d]
url: https://github.com/intel-lab-lkp/linux/commits/Jing-Zhang/KVM-arm64-Move-CPU-ID-feature-registers-emulation-into-a-separate-file/20230404-115612
base: 7e364e56293bb98cae1b55fd835f5991c4e96e7d
patch link: https://lore.kernel.org/r/20230404035344.4043856-5-jingzhangos%40google.com
patch subject: [PATCH v6 4/6] KVM: arm64: Use per guest ID register for ID_AA64DFR0_EL1.PMUVer
config: arm64-allyesconfig (https://download.01.org/0day-ci/archive/20230405/202304050006.49TmDWF6-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/66ece3020c02ab1206bb9478e8cb0172e125bbfc
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Jing-Zhang/KVM-arm64-Move-CPU-ID-feature-registers-emulation-into-a-separate-file/20230404-115612
git checkout 66ece3020c02ab1206bb9478e8cb0172e125bbfc
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm64 olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash arch/arm64/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202304050006.49TmDWF6-lkp@intel.com/
All errors (new ones prefixed by >>):
In file included from include/linux/rhashtable-types.h:14,
from include/linux/ipc.h:7,
from include/uapi/linux/sem.h:5,
from include/linux/sem.h:5,
from include/linux/sched.h:15,
from include/linux/hardirq.h:9,
from include/linux/kvm_host.h:7,
from arch/arm64/kvm/id_regs.c:13:
arch/arm64/kvm/id_regs.c: In function 'set_id_aa64dfr0_el1':
>> arch/arm64/kvm/id_regs.c:261:44: error: 'struct kvm_arch' has no member named 'config_lock'
261 | mutex_lock(&vcpu->kvm->arch.config_lock);
| ^
include/linux/mutex.h:187:44: note: in definition of macro 'mutex_lock'
187 | #define mutex_lock(lock) mutex_lock_nested(lock, 0)
| ^~~~
arch/arm64/kvm/id_regs.c:269:46: error: 'struct kvm_arch' has no member named 'config_lock'
269 | mutex_unlock(&vcpu->kvm->arch.config_lock);
| ^
arch/arm64/kvm/id_regs.c: In function 'set_id_dfr0_el1':
arch/arm64/kvm/id_regs.c:311:44: error: 'struct kvm_arch' has no member named 'config_lock'
311 | mutex_lock(&vcpu->kvm->arch.config_lock);
| ^
include/linux/mutex.h:187:44: note: in definition of macro 'mutex_lock'
187 | #define mutex_lock(lock) mutex_lock_nested(lock, 0)
| ^~~~
arch/arm64/kvm/id_regs.c:318:46: error: 'struct kvm_arch' has no member named 'config_lock'
318 | mutex_unlock(&vcpu->kvm->arch.config_lock);
| ^
vim +261 arch/arm64/kvm/id_regs.c
228
229 static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
230 const struct sys_reg_desc *rd,
231 u64 val)
232 {
233 u8 pmuver, host_pmuver;
234 bool valid_pmu;
235
236 host_pmuver = kvm_arm_pmu_get_pmuver_limit();
237
238 /*
239 * Allow AA64DFR0_EL1.PMUver to be set from userspace as long
240 * as it doesn't promise more than what the HW gives us. We
241 * allow an IMPDEF PMU though, only if no PMU is supported
242 * (KVM backward compatibility handling).
243 */
244 pmuver = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), val);
245 if ((pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF && pmuver > host_pmuver))
246 return -EINVAL;
247
248 valid_pmu = (pmuver != 0 && pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF);
249
250 /* Make sure view register and PMU support do match */
251 if (kvm_vcpu_has_pmu(vcpu) != valid_pmu)
252 return -EINVAL;
253
254 /* We can only differ with PMUver, and anything else is an error */
255 val ^= read_id_reg(vcpu, rd);
256 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
257 if (val)
258 return -EINVAL;
259
260 if (valid_pmu) {
> 261 mutex_lock(&vcpu->kvm->arch.config_lock);
262 IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
263 IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK,
264 pmuver);
265
266 IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &= ~ID_DFR0_EL1_PerfMon_MASK;
267 IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK,
268 pmuver_to_perfmon(pmuver));
269 mutex_unlock(&vcpu->kvm->arch.config_lock);
270 } else {
271 assign_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags,
272 pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF);
273 }
274
275 return 0;
276 }
277
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v6 4/6] KVM: arm64: Use per guest ID register for ID_AA64DFR0_EL1.PMUVer
2023-04-04 3:53 ` [PATCH v6 4/6] KVM: arm64: Use per guest ID register for ID_AA64DFR0_EL1.PMUVer Jing Zhang
2023-04-04 16:59 ` kernel test robot
@ 2023-04-11 6:47 ` kernel test robot
2023-04-19 3:40 ` Reiji Watanabe
2 siblings, 0 replies; 18+ messages in thread
From: kernel test robot @ 2023-04-11 6:47 UTC (permalink / raw)
To: Jing Zhang, KVM, KVMARM, ARMLinux, Marc Zyngier, Oliver Upton
Cc: llvm, oe-kbuild-all, Will Deacon, Paolo Bonzini, James Morse,
Alexandru Elisei, Suzuki K Poulose, Fuad Tabba, Reiji Watanabe,
Raghavendra Rao Ananta, Jing Zhang
Hi Jing,
kernel test robot noticed the following build errors:
[auto build test ERROR on 7e364e56293bb98cae1b55fd835f5991c4e96e7d]
url: https://github.com/intel-lab-lkp/linux/commits/Jing-Zhang/KVM-arm64-Move-CPU-ID-feature-registers-emulation-into-a-separate-file/20230404-115612
base: 7e364e56293bb98cae1b55fd835f5991c4e96e7d
patch link: https://lore.kernel.org/r/20230404035344.4043856-5-jingzhangos%40google.com
patch subject: [PATCH v6 4/6] KVM: arm64: Use per guest ID register for ID_AA64DFR0_EL1.PMUVer
config: arm64-randconfig-r031-20230410 (https://download.01.org/0day-ci/archive/20230411/202304111418.tQGXPpze-lkp@intel.com/config)
compiler: clang version 17.0.0 (https://github.com/llvm/llvm-project 2c57868e2e877f73c339796c3374ae660bb77f0d)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/66ece3020c02ab1206bb9478e8cb0172e125bbfc
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Jing-Zhang/KVM-arm64-Move-CPU-ID-feature-registers-emulation-into-a-separate-file/20230404-115612
git checkout 66ece3020c02ab1206bb9478e8cb0172e125bbfc
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash arch/arm64/kvm/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202304111418.tQGXPpze-lkp@intel.com/
All errors (new ones prefixed by >>):
>> arch/arm64/kvm/id_regs.c:261:31: error: no member named 'config_lock' in 'struct kvm_arch'
mutex_lock(&vcpu->kvm->arch.config_lock);
~~~~~~~~~~~~~~~ ^
include/linux/mutex.h:187:44: note: expanded from macro 'mutex_lock'
#define mutex_lock(lock) mutex_lock_nested(lock, 0)
^~~~
arch/arm64/kvm/id_regs.c:269:33: error: no member named 'config_lock' in 'struct kvm_arch'
mutex_unlock(&vcpu->kvm->arch.config_lock);
~~~~~~~~~~~~~~~ ^
arch/arm64/kvm/id_regs.c:311:31: error: no member named 'config_lock' in 'struct kvm_arch'
mutex_lock(&vcpu->kvm->arch.config_lock);
~~~~~~~~~~~~~~~ ^
include/linux/mutex.h:187:44: note: expanded from macro 'mutex_lock'
#define mutex_lock(lock) mutex_lock_nested(lock, 0)
^~~~
arch/arm64/kvm/id_regs.c:318:33: error: no member named 'config_lock' in 'struct kvm_arch'
mutex_unlock(&vcpu->kvm->arch.config_lock);
~~~~~~~~~~~~~~~ ^
4 errors generated.
vim +261 arch/arm64/kvm/id_regs.c
228
229 static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
230 const struct sys_reg_desc *rd,
231 u64 val)
232 {
233 u8 pmuver, host_pmuver;
234 bool valid_pmu;
235
236 host_pmuver = kvm_arm_pmu_get_pmuver_limit();
237
238 /*
239 * Allow AA64DFR0_EL1.PMUver to be set from userspace as long
240 * as it doesn't promise more than what the HW gives us. We
241 * allow an IMPDEF PMU though, only if no PMU is supported
242 * (KVM backward compatibility handling).
243 */
244 pmuver = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), val);
245 if ((pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF && pmuver > host_pmuver))
246 return -EINVAL;
247
248 valid_pmu = (pmuver != 0 && pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF);
249
250 /* Make sure view register and PMU support do match */
251 if (kvm_vcpu_has_pmu(vcpu) != valid_pmu)
252 return -EINVAL;
253
254 /* We can only differ with PMUver, and anything else is an error */
255 val ^= read_id_reg(vcpu, rd);
256 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
257 if (val)
258 return -EINVAL;
259
260 if (valid_pmu) {
> 261 mutex_lock(&vcpu->kvm->arch.config_lock);
262 IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
263 IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK,
264 pmuver);
265
266 IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &= ~ID_DFR0_EL1_PerfMon_MASK;
267 IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK,
268 pmuver_to_perfmon(pmuver));
269 mutex_unlock(&vcpu->kvm->arch.config_lock);
270 } else {
271 assign_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags,
272 pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF);
273 }
274
275 return 0;
276 }
277
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v6 4/6] KVM: arm64: Use per guest ID register for ID_AA64DFR0_EL1.PMUVer
2023-04-04 3:53 ` [PATCH v6 4/6] KVM: arm64: Use per guest ID register for ID_AA64DFR0_EL1.PMUVer Jing Zhang
2023-04-04 16:59 ` kernel test robot
2023-04-11 6:47 ` kernel test robot
@ 2023-04-19 3:40 ` Reiji Watanabe
2023-04-24 19:07 ` Jing Zhang
2 siblings, 1 reply; 18+ messages in thread
From: Reiji Watanabe @ 2023-04-19 3:40 UTC (permalink / raw)
To: Jing Zhang
Cc: KVM, KVMARM, ARMLinux, Marc Zyngier, Oliver Upton, Will Deacon,
Paolo Bonzini, James Morse, Alexandru Elisei, Suzuki K Poulose,
Fuad Tabba, Raghavendra Rao Ananta
Hi Jing,
On Tue, Apr 04, 2023 at 03:53:42AM +0000, Jing Zhang wrote:
> With per guest ID registers, PMUver settings from userspace
> can be stored in its corresponding ID register.
>
> No functional change intended.
>
> Signed-off-by: Jing Zhang <jingzhangos@google.com>
> ---
> arch/arm64/include/asm/kvm_host.h | 11 +++----
> arch/arm64/kvm/arm.c | 6 ----
> arch/arm64/kvm/id_regs.c | 50 ++++++++++++++++++++++++-------
> include/kvm/arm_pmu.h | 5 ++--
> 4 files changed, 49 insertions(+), 23 deletions(-)
>
> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
> index 67a55177fd83..da46a2729581 100644
> --- a/arch/arm64/include/asm/kvm_host.h
> +++ b/arch/arm64/include/asm/kvm_host.h
> @@ -237,6 +237,12 @@ struct kvm_arch {
> #define KVM_ARCH_FLAG_EL1_32BIT 4
> /* PSCI SYSTEM_SUSPEND enabled for the guest */
> #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 5
> + /*
> + * AA64DFR0_EL1.PMUver was set as ID_AA64DFR0_EL1_PMUVer_IMP_DEF
> + * or DFR0_EL1.PerfMon was set as ID_DFR0_EL1_PerfMon_IMPDEF from
> + * userspace for VCPUs without PMU.
> + */
> +#define KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU 6
>
> unsigned long flags;
>
> @@ -249,11 +255,6 @@ struct kvm_arch {
>
> cpumask_var_t supported_cpus;
>
> - struct {
> - u8 imp:4;
> - u8 unimp:4;
> - } dfr0_pmuver;
> -
> /* Hypercall features firmware registers' descriptor */
> struct kvm_smccc_features smccc_feat;
>
> diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
> index 64e1c19e5a9b..3fe28d545b54 100644
> --- a/arch/arm64/kvm/arm.c
> +++ b/arch/arm64/kvm/arm.c
> @@ -138,12 +138,6 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
> kvm_arm_init_hypercalls(kvm);
> kvm_arm_init_id_regs(kvm);
>
> - /*
> - * Initialise the default PMUver before there is a chance to
> - * create an actual PMU.
> - */
> - kvm->arch.dfr0_pmuver.imp = kvm_arm_pmu_get_pmuver_limit();
> -
> return 0;
>
> err_free_cpumask:
> diff --git a/arch/arm64/kvm/id_regs.c b/arch/arm64/kvm/id_regs.c
> index 291311b1ecca..6f65d30693fe 100644
> --- a/arch/arm64/kvm/id_regs.c
> +++ b/arch/arm64/kvm/id_regs.c
> @@ -21,9 +21,12 @@
> static u8 vcpu_pmuver(const struct kvm_vcpu *vcpu)
> {
> if (kvm_vcpu_has_pmu(vcpu))
> - return vcpu->kvm->arch.dfr0_pmuver.imp;
> + return FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer),
> + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1));
> + else if (test_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags))
> + return ID_AA64DFR0_EL1_PMUVer_IMP_DEF;
>
> - return vcpu->kvm->arch.dfr0_pmuver.unimp;
> + return 0;
> }
>
> static u8 perfmon_to_pmuver(u8 perfmon)
> @@ -254,10 +257,20 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
> if (val)
> return -EINVAL;
>
> - if (valid_pmu)
> - vcpu->kvm->arch.dfr0_pmuver.imp = pmuver;
> - else
> - vcpu->kvm->arch.dfr0_pmuver.unimp = pmuver;
> + if (valid_pmu) {
> + mutex_lock(&vcpu->kvm->arch.config_lock);
> + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
> + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK,
> + pmuver);
> +
> + IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &= ~ID_DFR0_EL1_PerfMon_MASK;
> + IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK,
> + pmuver_to_perfmon(pmuver));
As those could be read without acquiring the lock, I don't think
we should expose the intermediate state of the register values.
> + mutex_unlock(&vcpu->kvm->arch.config_lock);
> + } else {
> + assign_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags,
> + pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF);
> + }
>
> return 0;
> }
> @@ -294,10 +307,19 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
> if (val)
> return -EINVAL;
>
> - if (valid_pmu)
> - vcpu->kvm->arch.dfr0_pmuver.imp = perfmon_to_pmuver(perfmon);
> - else
> - vcpu->kvm->arch.dfr0_pmuver.unimp = perfmon_to_pmuver(perfmon);
> + if (valid_pmu) {
> + mutex_lock(&vcpu->kvm->arch.config_lock);
> + IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &= ~ID_DFR0_EL1_PerfMon_MASK;
> + IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK, perfmon);
> +
> + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
> + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK,
> + perfmon_to_pmuver(perfmon));
I have the same comment as set_id_aa64dfr0_el1().
Thank you,
Reiji
> + mutex_unlock(&vcpu->kvm->arch.config_lock);
> + } else {
> + assign_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags,
> + perfmon == ID_DFR0_EL1_PerfMon_IMPDEF);
> + }
>
> return 0;
> }
> @@ -503,4 +525,12 @@ void kvm_arm_init_id_regs(struct kvm *kvm)
> }
>
> IDREG(kvm, SYS_ID_AA64PFR0_EL1) = val;
> +
> + /*
> + * Initialise the default PMUver before there is a chance to
> + * create an actual PMU.
> + */
> + IDREG(kvm, SYS_ID_AA64DFR0_EL1) &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
> + IDREG(kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer),
> + kvm_arm_pmu_get_pmuver_limit());
> }
> diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
> index 628775334d5e..856ac59b6821 100644
> --- a/include/kvm/arm_pmu.h
> +++ b/include/kvm/arm_pmu.h
> @@ -92,8 +92,9 @@ void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu);
> /*
> * Evaluates as true when emulating PMUv3p5, and false otherwise.
> */
> -#define kvm_pmu_is_3p5(vcpu) \
> - (vcpu->kvm->arch.dfr0_pmuver.imp >= ID_AA64DFR0_EL1_PMUVer_V3P5)
> +#define kvm_pmu_is_3p5(vcpu) \
> + (FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), \
> + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1)) >= ID_AA64DFR0_EL1_PMUVer_V3P5)
>
> u8 kvm_arm_pmu_get_pmuver_limit(void);
>
> --
> 2.40.0.348.gf938b09366-goog
>
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v6 4/6] KVM: arm64: Use per guest ID register for ID_AA64DFR0_EL1.PMUVer
2023-04-19 3:40 ` Reiji Watanabe
@ 2023-04-24 19:07 ` Jing Zhang
2023-04-25 1:45 ` Reiji Watanabe
0 siblings, 1 reply; 18+ messages in thread
From: Jing Zhang @ 2023-04-24 19:07 UTC (permalink / raw)
To: Reiji Watanabe
Cc: KVM, KVMARM, ARMLinux, Marc Zyngier, Oliver Upton, Will Deacon,
Paolo Bonzini, James Morse, Alexandru Elisei, Suzuki K Poulose,
Fuad Tabba, Raghavendra Rao Ananta
Hi Reiji,
On Tue, Apr 18, 2023 at 8:40 PM Reiji Watanabe <reijiw@google.com> wrote:
>
> Hi Jing,
>
> On Tue, Apr 04, 2023 at 03:53:42AM +0000, Jing Zhang wrote:
> > With per guest ID registers, PMUver settings from userspace
> > can be stored in its corresponding ID register.
> >
> > No functional change intended.
> >
> > Signed-off-by: Jing Zhang <jingzhangos@google.com>
> > ---
> > arch/arm64/include/asm/kvm_host.h | 11 +++----
> > arch/arm64/kvm/arm.c | 6 ----
> > arch/arm64/kvm/id_regs.c | 50 ++++++++++++++++++++++++-------
> > include/kvm/arm_pmu.h | 5 ++--
> > 4 files changed, 49 insertions(+), 23 deletions(-)
> >
> > diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
> > index 67a55177fd83..da46a2729581 100644
> > --- a/arch/arm64/include/asm/kvm_host.h
> > +++ b/arch/arm64/include/asm/kvm_host.h
> > @@ -237,6 +237,12 @@ struct kvm_arch {
> > #define KVM_ARCH_FLAG_EL1_32BIT 4
> > /* PSCI SYSTEM_SUSPEND enabled for the guest */
> > #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 5
> > + /*
> > + * AA64DFR0_EL1.PMUver was set as ID_AA64DFR0_EL1_PMUVer_IMP_DEF
> > + * or DFR0_EL1.PerfMon was set as ID_DFR0_EL1_PerfMon_IMPDEF from
> > + * userspace for VCPUs without PMU.
> > + */
> > +#define KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU 6
> >
> > unsigned long flags;
> >
> > @@ -249,11 +255,6 @@ struct kvm_arch {
> >
> > cpumask_var_t supported_cpus;
> >
> > - struct {
> > - u8 imp:4;
> > - u8 unimp:4;
> > - } dfr0_pmuver;
> > -
> > /* Hypercall features firmware registers' descriptor */
> > struct kvm_smccc_features smccc_feat;
> >
> > diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
> > index 64e1c19e5a9b..3fe28d545b54 100644
> > --- a/arch/arm64/kvm/arm.c
> > +++ b/arch/arm64/kvm/arm.c
> > @@ -138,12 +138,6 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
> > kvm_arm_init_hypercalls(kvm);
> > kvm_arm_init_id_regs(kvm);
> >
> > - /*
> > - * Initialise the default PMUver before there is a chance to
> > - * create an actual PMU.
> > - */
> > - kvm->arch.dfr0_pmuver.imp = kvm_arm_pmu_get_pmuver_limit();
> > -
> > return 0;
> >
> > err_free_cpumask:
> > diff --git a/arch/arm64/kvm/id_regs.c b/arch/arm64/kvm/id_regs.c
> > index 291311b1ecca..6f65d30693fe 100644
> > --- a/arch/arm64/kvm/id_regs.c
> > +++ b/arch/arm64/kvm/id_regs.c
> > @@ -21,9 +21,12 @@
> > static u8 vcpu_pmuver(const struct kvm_vcpu *vcpu)
> > {
> > if (kvm_vcpu_has_pmu(vcpu))
> > - return vcpu->kvm->arch.dfr0_pmuver.imp;
> > + return FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer),
> > + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1));
> > + else if (test_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags))
> > + return ID_AA64DFR0_EL1_PMUVer_IMP_DEF;
> >
> > - return vcpu->kvm->arch.dfr0_pmuver.unimp;
> > + return 0;
> > }
> >
> > static u8 perfmon_to_pmuver(u8 perfmon)
> > @@ -254,10 +257,20 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
> > if (val)
> > return -EINVAL;
> >
> > - if (valid_pmu)
> > - vcpu->kvm->arch.dfr0_pmuver.imp = pmuver;
> > - else
> > - vcpu->kvm->arch.dfr0_pmuver.unimp = pmuver;
> > + if (valid_pmu) {
> > + mutex_lock(&vcpu->kvm->arch.config_lock);
> > + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
> > + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK,
> > + pmuver);
> > +
> > + IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &= ~ID_DFR0_EL1_PerfMon_MASK;
> > + IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK,
> > + pmuver_to_perfmon(pmuver));
>
> As those could be read without acquiring the lock, I don't think
> we should expose the intermediate state of the register values.
I will protect all reads/writes to KVM scope emulated ID registers
with the lock.
>
>
> > + mutex_unlock(&vcpu->kvm->arch.config_lock);
> > + } else {
> > + assign_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags,
> > + pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF);
> > + }
> >
> > return 0;
> > }
> > @@ -294,10 +307,19 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
> > if (val)
> > return -EINVAL;
> >
> > - if (valid_pmu)
> > - vcpu->kvm->arch.dfr0_pmuver.imp = perfmon_to_pmuver(perfmon);
> > - else
> > - vcpu->kvm->arch.dfr0_pmuver.unimp = perfmon_to_pmuver(perfmon);
> > + if (valid_pmu) {
> > + mutex_lock(&vcpu->kvm->arch.config_lock);
> > + IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &= ~ID_DFR0_EL1_PerfMon_MASK;
> > + IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK, perfmon);
> > +
> > + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
> > + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK,
> > + perfmon_to_pmuver(perfmon));
>
> I have the same comment as set_id_aa64dfr0_el1().
>
> Thank you,
> Reiji
>
> > + mutex_unlock(&vcpu->kvm->arch.config_lock);
> > + } else {
> > + assign_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags,
> > + perfmon == ID_DFR0_EL1_PerfMon_IMPDEF);
> > + }
> >
> > return 0;
> > }
> > @@ -503,4 +525,12 @@ void kvm_arm_init_id_regs(struct kvm *kvm)
> > }
> >
> > IDREG(kvm, SYS_ID_AA64PFR0_EL1) = val;
> > +
> > + /*
> > + * Initialise the default PMUver before there is a chance to
> > + * create an actual PMU.
> > + */
> > + IDREG(kvm, SYS_ID_AA64DFR0_EL1) &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
> > + IDREG(kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer),
> > + kvm_arm_pmu_get_pmuver_limit());
> > }
> > diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
> > index 628775334d5e..856ac59b6821 100644
> > --- a/include/kvm/arm_pmu.h
> > +++ b/include/kvm/arm_pmu.h
> > @@ -92,8 +92,9 @@ void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu);
> > /*
> > * Evaluates as true when emulating PMUv3p5, and false otherwise.
> > */
> > -#define kvm_pmu_is_3p5(vcpu) \
> > - (vcpu->kvm->arch.dfr0_pmuver.imp >= ID_AA64DFR0_EL1_PMUVer_V3P5)
> > +#define kvm_pmu_is_3p5(vcpu) \
> > + (FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), \
> > + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1)) >= ID_AA64DFR0_EL1_PMUVer_V3P5)
> >
> > u8 kvm_arm_pmu_get_pmuver_limit(void);
> >
> > --
> > 2.40.0.348.gf938b09366-goog
> >
Thanks,
Jing
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v6 4/6] KVM: arm64: Use per guest ID register for ID_AA64DFR0_EL1.PMUVer
2023-04-24 19:07 ` Jing Zhang
@ 2023-04-25 1:45 ` Reiji Watanabe
0 siblings, 0 replies; 18+ messages in thread
From: Reiji Watanabe @ 2023-04-25 1:45 UTC (permalink / raw)
To: Jing Zhang
Cc: KVM, KVMARM, ARMLinux, Marc Zyngier, Oliver Upton, Will Deacon,
Paolo Bonzini, James Morse, Alexandru Elisei, Suzuki K Poulose,
Fuad Tabba, Raghavendra Rao Ananta
Hi Jing,
On Mon, Apr 24, 2023 at 12:07:31PM -0700, Jing Zhang wrote:
> Hi Reiji,
>
> On Tue, Apr 18, 2023 at 8:40 PM Reiji Watanabe <reijiw@google.com> wrote:
> >
> > Hi Jing,
> >
> > On Tue, Apr 04, 2023 at 03:53:42AM +0000, Jing Zhang wrote:
> > > With per guest ID registers, PMUver settings from userspace
> > > can be stored in its corresponding ID register.
> > >
> > > No functional change intended.
> > >
> > > Signed-off-by: Jing Zhang <jingzhangos@google.com>
> > > ---
> > > arch/arm64/include/asm/kvm_host.h | 11 +++----
> > > arch/arm64/kvm/arm.c | 6 ----
> > > arch/arm64/kvm/id_regs.c | 50 ++++++++++++++++++++++++-------
> > > include/kvm/arm_pmu.h | 5 ++--
> > > 4 files changed, 49 insertions(+), 23 deletions(-)
> > >
> > > diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
> > > index 67a55177fd83..da46a2729581 100644
> > > --- a/arch/arm64/include/asm/kvm_host.h
> > > +++ b/arch/arm64/include/asm/kvm_host.h
> > > @@ -237,6 +237,12 @@ struct kvm_arch {
> > > #define KVM_ARCH_FLAG_EL1_32BIT 4
> > > /* PSCI SYSTEM_SUSPEND enabled for the guest */
> > > #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 5
> > > + /*
> > > + * AA64DFR0_EL1.PMUver was set as ID_AA64DFR0_EL1_PMUVer_IMP_DEF
> > > + * or DFR0_EL1.PerfMon was set as ID_DFR0_EL1_PerfMon_IMPDEF from
> > > + * userspace for VCPUs without PMU.
> > > + */
> > > +#define KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU 6
> > >
> > > unsigned long flags;
> > >
> > > @@ -249,11 +255,6 @@ struct kvm_arch {
> > >
> > > cpumask_var_t supported_cpus;
> > >
> > > - struct {
> > > - u8 imp:4;
> > > - u8 unimp:4;
> > > - } dfr0_pmuver;
> > > -
> > > /* Hypercall features firmware registers' descriptor */
> > > struct kvm_smccc_features smccc_feat;
> > >
> > > diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
> > > index 64e1c19e5a9b..3fe28d545b54 100644
> > > --- a/arch/arm64/kvm/arm.c
> > > +++ b/arch/arm64/kvm/arm.c
> > > @@ -138,12 +138,6 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
> > > kvm_arm_init_hypercalls(kvm);
> > > kvm_arm_init_id_regs(kvm);
> > >
> > > - /*
> > > - * Initialise the default PMUver before there is a chance to
> > > - * create an actual PMU.
> > > - */
> > > - kvm->arch.dfr0_pmuver.imp = kvm_arm_pmu_get_pmuver_limit();
> > > -
> > > return 0;
> > >
> > > err_free_cpumask:
> > > diff --git a/arch/arm64/kvm/id_regs.c b/arch/arm64/kvm/id_regs.c
> > > index 291311b1ecca..6f65d30693fe 100644
> > > --- a/arch/arm64/kvm/id_regs.c
> > > +++ b/arch/arm64/kvm/id_regs.c
> > > @@ -21,9 +21,12 @@
> > > static u8 vcpu_pmuver(const struct kvm_vcpu *vcpu)
> > > {
> > > if (kvm_vcpu_has_pmu(vcpu))
> > > - return vcpu->kvm->arch.dfr0_pmuver.imp;
> > > + return FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer),
> > > + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1));
> > > + else if (test_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags))
> > > + return ID_AA64DFR0_EL1_PMUVer_IMP_DEF;
> > >
> > > - return vcpu->kvm->arch.dfr0_pmuver.unimp;
> > > + return 0;
> > > }
> > >
> > > static u8 perfmon_to_pmuver(u8 perfmon)
> > > @@ -254,10 +257,20 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
> > > if (val)
> > > return -EINVAL;
> > >
> > > - if (valid_pmu)
> > > - vcpu->kvm->arch.dfr0_pmuver.imp = pmuver;
> > > - else
> > > - vcpu->kvm->arch.dfr0_pmuver.unimp = pmuver;
> > > + if (valid_pmu) {
> > > + mutex_lock(&vcpu->kvm->arch.config_lock);
> > > + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
> > > + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK,
> > > + pmuver);
> > > +
> > > + IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &= ~ID_DFR0_EL1_PerfMon_MASK;
> > > + IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK,
> > > + pmuver_to_perfmon(pmuver));
> >
> > As those could be read without acquiring the lock, I don't think
> > we should expose the intermediate state of the register values.
> I will protect all reads/writes to KVM scope emulated ID registers
> with the lock.
Or I think we could resolve it by writing the new value atomically
(copy the value to a local variable, set the local variable to the
new value, and update the ID_REG value with WRITE_ONCE).
Thank you,
Reiji
> >
> >
> > > + mutex_unlock(&vcpu->kvm->arch.config_lock);
> > > + } else {
> > > + assign_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags,
> > > + pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF);
> > > + }
> > >
> > > return 0;
> > > }
> > > @@ -294,10 +307,19 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
> > > if (val)
> > > return -EINVAL;
> > >
> > > - if (valid_pmu)
> > > - vcpu->kvm->arch.dfr0_pmuver.imp = perfmon_to_pmuver(perfmon);
> > > - else
> > > - vcpu->kvm->arch.dfr0_pmuver.unimp = perfmon_to_pmuver(perfmon);
> > > + if (valid_pmu) {
> > > + mutex_lock(&vcpu->kvm->arch.config_lock);
> > > + IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &= ~ID_DFR0_EL1_PerfMon_MASK;
> > > + IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK, perfmon);
> > > +
> > > + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
> > > + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK,
> > > + perfmon_to_pmuver(perfmon));
> >
> > I have the same comment as set_id_aa64dfr0_el1().
> >
> > Thank you,
> > Reiji
> >
> > > + mutex_unlock(&vcpu->kvm->arch.config_lock);
> > > + } else {
> > > + assign_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags,
> > > + perfmon == ID_DFR0_EL1_PerfMon_IMPDEF);
> > > + }
> > >
> > > return 0;
> > > }
> > > @@ -503,4 +525,12 @@ void kvm_arm_init_id_regs(struct kvm *kvm)
> > > }
> > >
> > > IDREG(kvm, SYS_ID_AA64PFR0_EL1) = val;
> > > +
> > > + /*
> > > + * Initialise the default PMUver before there is a chance to
> > > + * create an actual PMU.
> > > + */
> > > + IDREG(kvm, SYS_ID_AA64DFR0_EL1) &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
> > > + IDREG(kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer),
> > > + kvm_arm_pmu_get_pmuver_limit());
> > > }
> > > diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
> > > index 628775334d5e..856ac59b6821 100644
> > > --- a/include/kvm/arm_pmu.h
> > > +++ b/include/kvm/arm_pmu.h
> > > @@ -92,8 +92,9 @@ void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu);
> > > /*
> > > * Evaluates as true when emulating PMUv3p5, and false otherwise.
> > > */
> > > -#define kvm_pmu_is_3p5(vcpu) \
> > > - (vcpu->kvm->arch.dfr0_pmuver.imp >= ID_AA64DFR0_EL1_PMUVer_V3P5)
> > > +#define kvm_pmu_is_3p5(vcpu) \
> > > + (FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), \
> > > + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1)) >= ID_AA64DFR0_EL1_PMUVer_V3P5)
> > >
> > > u8 kvm_arm_pmu_get_pmuver_limit(void);
> > >
> > > --
> > > 2.40.0.348.gf938b09366-goog
> > >
> Thanks,
> Jing
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^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v6 5/6] KVM: arm64: Reuse fields of sys_reg_desc for idreg
2023-04-04 3:53 [PATCH v6 0/6] Support writable CPU ID registers from userspace Jing Zhang
` (3 preceding siblings ...)
2023-04-04 3:53 ` [PATCH v6 4/6] KVM: arm64: Use per guest ID register for ID_AA64DFR0_EL1.PMUVer Jing Zhang
@ 2023-04-04 3:53 ` Jing Zhang
2023-04-19 4:09 ` Reiji Watanabe
2023-04-04 3:53 ` [PATCH v6 6/6] KVM: arm64: Refactor writings for PMUVer/CSV2/CSV3 Jing Zhang
5 siblings, 1 reply; 18+ messages in thread
From: Jing Zhang @ 2023-04-04 3:53 UTC (permalink / raw)
To: KVM, KVMARM, ARMLinux, Marc Zyngier, Oliver Upton
Cc: Will Deacon, Paolo Bonzini, James Morse, Alexandru Elisei,
Suzuki K Poulose, Fuad Tabba, Reiji Watanabe,
Raghavendra Rao Ananta, Jing Zhang
Since reset() and val are not used for idreg in sys_reg_desc, they would
be used with other purposes for idregs.
The callback reset() would be used to return KVM sanitised id register
values. The u64 val would be used as mask for writable fields in idregs.
Only bits with 1 in val are writable from userspace.
Signed-off-by: Jing Zhang <jingzhangos@google.com>
---
arch/arm64/kvm/id_regs.c | 44 +++++++++++++++++++----------
arch/arm64/kvm/sys_regs.c | 59 +++++++++++++++++++++++++++------------
arch/arm64/kvm/sys_regs.h | 10 ++++---
3 files changed, 77 insertions(+), 36 deletions(-)
diff --git a/arch/arm64/kvm/id_regs.c b/arch/arm64/kvm/id_regs.c
index 6f65d30693fe..fe37b6786b4c 100644
--- a/arch/arm64/kvm/id_regs.c
+++ b/arch/arm64/kvm/id_regs.c
@@ -55,6 +55,11 @@ static u8 pmuver_to_perfmon(u8 pmuver)
}
}
+static u64 general_read_kvm_sanitised_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd)
+{
+ return read_sanitised_ftr_reg(reg_to_encoding(rd));
+}
+
u64 kvm_arm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id)
{
u64 val = IDREG(vcpu->kvm, id);
@@ -324,6 +329,17 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
return 0;
}
+/*
+ * Since reset() callback and field val are not used for idregs, they will be
+ * used for specific purposes for idregs.
+ * The reset() would return KVM sanitised register value. The value would be the
+ * same as the host kernel sanitised value if there is no KVM sanitisation.
+ * The val would be used as a mask indicating writable fields for the idreg.
+ * Only bits with 1 are writable from userspace. This mask might not be
+ * necessary in the future whenever all ID registers are enabled as writable
+ * from userspace.
+ */
+
/* sys_reg_desc initialiser for known cpufeature ID registers */
#define ID_SANITISED(name) { \
SYS_DESC(SYS_##name), \
@@ -331,6 +347,8 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
.get_user = get_id_reg, \
.set_user = set_id_reg, \
.visibility = id_visibility, \
+ .reset = general_read_kvm_sanitised_reg,\
+ .val = 0, \
}
/* sys_reg_desc initialiser for known cpufeature ID registers */
@@ -340,6 +358,8 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
.get_user = get_id_reg, \
.set_user = set_id_reg, \
.visibility = aa32_id_visibility, \
+ .reset = general_read_kvm_sanitised_reg,\
+ .val = 0, \
}
/*
@@ -352,7 +372,9 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
.access = access_id_reg, \
.get_user = get_id_reg, \
.set_user = set_id_reg, \
- .visibility = raz_visibility \
+ .visibility = raz_visibility, \
+ .reset = NULL, \
+ .val = 0, \
}
/*
@@ -366,6 +388,8 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
.get_user = get_id_reg, \
.set_user = set_id_reg, \
.visibility = raz_visibility, \
+ .reset = NULL, \
+ .val = 0, \
}
const struct sys_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = {
@@ -476,10 +500,7 @@ int emulate_id_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params)
return 1;
}
-/*
- * Set the guest's ID registers that are defined in id_reg_descs[]
- * with ID_SANITISED() to the host's sanitized value.
- */
+/* Initialize the guest's ID registers with KVM sanitised values. */
void kvm_arm_init_id_regs(struct kvm *kvm)
{
int i;
@@ -492,16 +513,11 @@ void kvm_arm_init_id_regs(struct kvm *kvm)
/* Shouldn't happen */
continue;
- /*
- * Some hidden ID registers which are not in arm64_ftr_regs[]
- * would cause warnings from read_sanitised_ftr_reg().
- * Skip those ID registers to avoid the warnings.
- */
- if (id_reg_descs[i].visibility == raz_visibility)
- /* Hidden or reserved ID register */
- continue;
+ val = 0;
+ /* Read KVM sanitised register value if available */
+ if (id_reg_descs[i].reset)
+ val = id_reg_descs[i].reset(NULL, &id_reg_descs[i]);
- val = read_sanitised_ftr_reg(id);
IDREG(kvm, id) = val;
}
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 15979c2b87ab..703cf833345a 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -540,10 +540,11 @@ static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
return 0;
}
-static void reset_bvr(struct kvm_vcpu *vcpu,
+static u64 reset_bvr(struct kvm_vcpu *vcpu,
const struct sys_reg_desc *rd)
{
vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val;
+ return rd->val;
}
static bool trap_bcr(struct kvm_vcpu *vcpu,
@@ -576,10 +577,11 @@ static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
return 0;
}
-static void reset_bcr(struct kvm_vcpu *vcpu,
+static u64 reset_bcr(struct kvm_vcpu *vcpu,
const struct sys_reg_desc *rd)
{
vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val;
+ return rd->val;
}
static bool trap_wvr(struct kvm_vcpu *vcpu,
@@ -613,10 +615,11 @@ static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
return 0;
}
-static void reset_wvr(struct kvm_vcpu *vcpu,
+static u64 reset_wvr(struct kvm_vcpu *vcpu,
const struct sys_reg_desc *rd)
{
vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val;
+ return rd->val;
}
static bool trap_wcr(struct kvm_vcpu *vcpu,
@@ -649,25 +652,28 @@ static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
return 0;
}
-static void reset_wcr(struct kvm_vcpu *vcpu,
+static u64 reset_wcr(struct kvm_vcpu *vcpu,
const struct sys_reg_desc *rd)
{
vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val;
+ return rd->val;
}
-static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
+static u64 reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
{
u64 amair = read_sysreg(amair_el1);
vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1);
+ return amair;
}
-static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
+static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
{
u64 actlr = read_sysreg(actlr_el1);
vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1);
+ return actlr;
}
-static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
+static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
{
u64 mpidr;
@@ -681,7 +687,10 @@ static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
- vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1);
+ mpidr |= (1ULL << 31);
+ vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1);
+
+ return mpidr;
}
static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu,
@@ -693,13 +702,13 @@ static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu,
return REG_HIDDEN;
}
-static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
+static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
{
u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX);
/* No PMU available, any PMU reg may UNDEF... */
if (!kvm_arm_support_pmu_v3())
- return;
+ return 0;
n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT;
n &= ARMV8_PMU_PMCR_N_MASK;
@@ -708,33 +717,41 @@ static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
reset_unknown(vcpu, r);
__vcpu_sys_reg(vcpu, r->reg) &= mask;
+
+ return __vcpu_sys_reg(vcpu, r->reg);
}
-static void reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
+static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
{
reset_unknown(vcpu, r);
__vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0);
+
+ return __vcpu_sys_reg(vcpu, r->reg);
}
-static void reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
+static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
{
reset_unknown(vcpu, r);
__vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_EVTYPE_MASK;
+
+ return __vcpu_sys_reg(vcpu, r->reg);
}
-static void reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
+static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
{
reset_unknown(vcpu, r);
__vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_COUNTER_MASK;
+
+ return __vcpu_sys_reg(vcpu, r->reg);
}
-static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
+static u64 reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
{
u64 pmcr;
/* No PMU available, PMCR_EL0 may UNDEF... */
if (!kvm_arm_support_pmu_v3())
- return;
+ return 0;
/* Only preserve PMCR_EL0.N, and reset the rest to 0 */
pmcr = read_sysreg(pmcr_el0) & (ARMV8_PMU_PMCR_N_MASK << ARMV8_PMU_PMCR_N_SHIFT);
@@ -742,6 +759,8 @@ static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
pmcr |= ARMV8_PMU_PMCR_LC;
__vcpu_sys_reg(vcpu, r->reg) = pmcr;
+
+ return __vcpu_sys_reg(vcpu, r->reg);
}
static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
@@ -1221,7 +1240,7 @@ static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
* Fabricate a CLIDR_EL1 value instead of using the real value, which can vary
* by the physical CPU which the vcpu currently resides in.
*/
-static void reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
+static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
{
u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0);
u64 clidr;
@@ -1269,6 +1288,8 @@ static void reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
clidr |= 2 << CLIDR_TTYPE_SHIFT(loc);
__vcpu_sys_reg(vcpu, r->reg) = clidr;
+
+ return __vcpu_sys_reg(vcpu, r->reg);
}
static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
@@ -2622,19 +2643,21 @@ id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id,
*/
#define FUNCTION_INVARIANT(reg) \
- static void get_##reg(struct kvm_vcpu *v, \
+ static u64 get_##reg(struct kvm_vcpu *v, \
const struct sys_reg_desc *r) \
{ \
((struct sys_reg_desc *)r)->val = read_sysreg(reg); \
+ return ((struct sys_reg_desc *)r)->val; \
}
FUNCTION_INVARIANT(midr_el1)
FUNCTION_INVARIANT(revidr_el1)
FUNCTION_INVARIANT(aidr_el1)
-static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r)
+static u64 get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r)
{
((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0);
+ return ((struct sys_reg_desc *)r)->val;
}
/* ->val is filled in by kvm_sys_reg_table_init() */
diff --git a/arch/arm64/kvm/sys_regs.h b/arch/arm64/kvm/sys_regs.h
index e88fd77309b2..21869319f6e1 100644
--- a/arch/arm64/kvm/sys_regs.h
+++ b/arch/arm64/kvm/sys_regs.h
@@ -65,12 +65,12 @@ struct sys_reg_desc {
const struct sys_reg_desc *);
/* Initialization for vcpu. */
- void (*reset)(struct kvm_vcpu *, const struct sys_reg_desc *);
+ u64 (*reset)(struct kvm_vcpu *, const struct sys_reg_desc *);
/* Index into sys_reg[], or 0 if we don't need to save it. */
int reg;
- /* Value (usually reset value) */
+ /* Value (usually reset value), or write mask for idregs */
u64 val;
/* Custom get/set_user functions, fallback to generic if NULL */
@@ -123,19 +123,21 @@ static inline bool read_zero(struct kvm_vcpu *vcpu,
}
/* Reset functions */
-static inline void reset_unknown(struct kvm_vcpu *vcpu,
+static inline u64 reset_unknown(struct kvm_vcpu *vcpu,
const struct sys_reg_desc *r)
{
BUG_ON(!r->reg);
BUG_ON(r->reg >= NR_SYS_REGS);
__vcpu_sys_reg(vcpu, r->reg) = 0x1de7ec7edbadc0deULL;
+ return __vcpu_sys_reg(vcpu, r->reg);
}
-static inline void reset_val(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
+static inline u64 reset_val(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
{
BUG_ON(!r->reg);
BUG_ON(r->reg >= NR_SYS_REGS);
__vcpu_sys_reg(vcpu, r->reg) = r->val;
+ return __vcpu_sys_reg(vcpu, r->reg);
}
static inline unsigned int sysreg_visibility(const struct kvm_vcpu *vcpu,
--
2.40.0.348.gf938b09366-goog
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v6 5/6] KVM: arm64: Reuse fields of sys_reg_desc for idreg
2023-04-04 3:53 ` [PATCH v6 5/6] KVM: arm64: Reuse fields of sys_reg_desc for idreg Jing Zhang
@ 2023-04-19 4:09 ` Reiji Watanabe
2023-04-24 19:12 ` Jing Zhang
0 siblings, 1 reply; 18+ messages in thread
From: Reiji Watanabe @ 2023-04-19 4:09 UTC (permalink / raw)
To: Jing Zhang
Cc: KVM, KVMARM, ARMLinux, Marc Zyngier, Oliver Upton, Will Deacon,
Paolo Bonzini, James Morse, Alexandru Elisei, Suzuki K Poulose,
Fuad Tabba, Raghavendra Rao Ananta
Hi Jing,
On Tue, Apr 04, 2023 at 03:53:43AM +0000, Jing Zhang wrote:
> Since reset() and val are not used for idreg in sys_reg_desc, they would
> be used with other purposes for idregs.
> The callback reset() would be used to return KVM sanitised id register
> values. The u64 val would be used as mask for writable fields in idregs.
> Only bits with 1 in val are writable from userspace.
>
> Signed-off-by: Jing Zhang <jingzhangos@google.com>
> ---
> arch/arm64/kvm/id_regs.c | 44 +++++++++++++++++++----------
> arch/arm64/kvm/sys_regs.c | 59 +++++++++++++++++++++++++++------------
> arch/arm64/kvm/sys_regs.h | 10 ++++---
> 3 files changed, 77 insertions(+), 36 deletions(-)
>
> diff --git a/arch/arm64/kvm/id_regs.c b/arch/arm64/kvm/id_regs.c
> index 6f65d30693fe..fe37b6786b4c 100644
> --- a/arch/arm64/kvm/id_regs.c
> +++ b/arch/arm64/kvm/id_regs.c
> @@ -55,6 +55,11 @@ static u8 pmuver_to_perfmon(u8 pmuver)
> }
> }
>
> +static u64 general_read_kvm_sanitised_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd)
> +{
> + return read_sanitised_ftr_reg(reg_to_encoding(rd));
> +}
> +
> u64 kvm_arm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id)
> {
> u64 val = IDREG(vcpu->kvm, id);
> @@ -324,6 +329,17 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
> return 0;
> }
>
> +/*
> + * Since reset() callback and field val are not used for idregs, they will be
> + * used for specific purposes for idregs.
> + * The reset() would return KVM sanitised register value. The value would be the
> + * same as the host kernel sanitised value if there is no KVM sanitisation.
> + * The val would be used as a mask indicating writable fields for the idreg.
> + * Only bits with 1 are writable from userspace. This mask might not be
Nit: This comment update seems to be in the next patch,
since 'val' for AA64PFR0, AA64DFR0 and DFR0 is zero yet.
> + * necessary in the future whenever all ID registers are enabled as writable
> + * from userspace.
> + */
> +
> /* sys_reg_desc initialiser for known cpufeature ID registers */
> #define ID_SANITISED(name) { \
> SYS_DESC(SYS_##name), \
> @@ -331,6 +347,8 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
> .get_user = get_id_reg, \
> .set_user = set_id_reg, \
> .visibility = id_visibility, \
> + .reset = general_read_kvm_sanitised_reg,\
> + .val = 0, \
> }
>
> /* sys_reg_desc initialiser for known cpufeature ID registers */
> @@ -340,6 +358,8 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
> .get_user = get_id_reg, \
> .set_user = set_id_reg, \
> .visibility = aa32_id_visibility, \
> + .reset = general_read_kvm_sanitised_reg,\
> + .val = 0, \
> }
>
> /*
> @@ -352,7 +372,9 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
> .access = access_id_reg, \
> .get_user = get_id_reg, \
> .set_user = set_id_reg, \
> - .visibility = raz_visibility \
> + .visibility = raz_visibility, \
> + .reset = NULL, \
> + .val = 0, \
> }
>
> /*
> @@ -366,6 +388,8 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
> .get_user = get_id_reg, \
> .set_user = set_id_reg, \
> .visibility = raz_visibility, \
> + .reset = NULL, \
> + .val = 0, \
> }
>
> const struct sys_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = {
> @@ -476,10 +500,7 @@ int emulate_id_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params)
> return 1;
> }
>
> -/*
> - * Set the guest's ID registers that are defined in id_reg_descs[]
> - * with ID_SANITISED() to the host's sanitized value.
> - */
> +/* Initialize the guest's ID registers with KVM sanitised values. */
> void kvm_arm_init_id_regs(struct kvm *kvm)
> {
> int i;
> @@ -492,16 +513,11 @@ void kvm_arm_init_id_regs(struct kvm *kvm)
> /* Shouldn't happen */
> continue;
>
> - /*
> - * Some hidden ID registers which are not in arm64_ftr_regs[]
> - * would cause warnings from read_sanitised_ftr_reg().
> - * Skip those ID registers to avoid the warnings.
> - */
> - if (id_reg_descs[i].visibility == raz_visibility)
> - /* Hidden or reserved ID register */
> - continue;
> + val = 0;
> + /* Read KVM sanitised register value if available */
> + if (id_reg_descs[i].reset)
> + val = id_reg_descs[i].reset(NULL, &id_reg_descs[i]);
>
> - val = read_sanitised_ftr_reg(id);
> IDREG(kvm, id) = val;
> }
>
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index 15979c2b87ab..703cf833345a 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -540,10 +540,11 @@ static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
> return 0;
> }
>
> -static void reset_bvr(struct kvm_vcpu *vcpu,
> +static u64 reset_bvr(struct kvm_vcpu *vcpu,
> const struct sys_reg_desc *rd)
> {
> vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val;
> + return rd->val;
> }
>
> static bool trap_bcr(struct kvm_vcpu *vcpu,
> @@ -576,10 +577,11 @@ static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
> return 0;
> }
>
> -static void reset_bcr(struct kvm_vcpu *vcpu,
> +static u64 reset_bcr(struct kvm_vcpu *vcpu,
> const struct sys_reg_desc *rd)
> {
> vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val;
> + return rd->val;
> }
>
> static bool trap_wvr(struct kvm_vcpu *vcpu,
> @@ -613,10 +615,11 @@ static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
> return 0;
> }
>
> -static void reset_wvr(struct kvm_vcpu *vcpu,
> +static u64 reset_wvr(struct kvm_vcpu *vcpu,
> const struct sys_reg_desc *rd)
> {
> vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val;
> + return rd->val;
> }
>
> static bool trap_wcr(struct kvm_vcpu *vcpu,
> @@ -649,25 +652,28 @@ static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
> return 0;
> }
>
> -static void reset_wcr(struct kvm_vcpu *vcpu,
> +static u64 reset_wcr(struct kvm_vcpu *vcpu,
> const struct sys_reg_desc *rd)
> {
> vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val;
> + return rd->val;
> }
>
> -static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> +static u64 reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> {
> u64 amair = read_sysreg(amair_el1);
> vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1);
> + return amair;
> }
>
> -static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> +static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> {
> u64 actlr = read_sysreg(actlr_el1);
> vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1);
> + return actlr;
> }
>
> -static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> +static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> {
> u64 mpidr;
>
> @@ -681,7 +687,10 @@ static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
> mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
> mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
> - vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1);
> + mpidr |= (1ULL << 31);
> + vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1);
> +
> + return mpidr;
> }
>
> static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu,
> @@ -693,13 +702,13 @@ static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu,
> return REG_HIDDEN;
> }
>
> -static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> +static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> {
> u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX);
>
> /* No PMU available, any PMU reg may UNDEF... */
> if (!kvm_arm_support_pmu_v3())
> - return;
> + return 0;
>
> n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT;
> n &= ARMV8_PMU_PMCR_N_MASK;
> @@ -708,33 +717,41 @@ static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
>
> reset_unknown(vcpu, r);
> __vcpu_sys_reg(vcpu, r->reg) &= mask;
> +
> + return __vcpu_sys_reg(vcpu, r->reg);
> }
>
> -static void reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> +static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> {
> reset_unknown(vcpu, r);
> __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0);
> +
> + return __vcpu_sys_reg(vcpu, r->reg);
> }
>
> -static void reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> +static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> {
> reset_unknown(vcpu, r);
> __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_EVTYPE_MASK;
> +
> + return __vcpu_sys_reg(vcpu, r->reg);
> }
>
> -static void reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> +static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> {
> reset_unknown(vcpu, r);
> __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_COUNTER_MASK;
> +
> + return __vcpu_sys_reg(vcpu, r->reg);
> }
>
> -static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> +static u64 reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> {
> u64 pmcr;
>
> /* No PMU available, PMCR_EL0 may UNDEF... */
> if (!kvm_arm_support_pmu_v3())
> - return;
> + return 0;
>
> /* Only preserve PMCR_EL0.N, and reset the rest to 0 */
> pmcr = read_sysreg(pmcr_el0) & (ARMV8_PMU_PMCR_N_MASK << ARMV8_PMU_PMCR_N_SHIFT);
> @@ -742,6 +759,8 @@ static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> pmcr |= ARMV8_PMU_PMCR_LC;
>
> __vcpu_sys_reg(vcpu, r->reg) = pmcr;
> +
> + return __vcpu_sys_reg(vcpu, r->reg);
> }
>
> static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
> @@ -1221,7 +1240,7 @@ static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
> * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary
> * by the physical CPU which the vcpu currently resides in.
> */
> -static void reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> +static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> {
> u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0);
> u64 clidr;
> @@ -1269,6 +1288,8 @@ static void reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> clidr |= 2 << CLIDR_TTYPE_SHIFT(loc);
>
> __vcpu_sys_reg(vcpu, r->reg) = clidr;
> +
> + return __vcpu_sys_reg(vcpu, r->reg);
> }
>
> static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
> @@ -2622,19 +2643,21 @@ id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id,
> */
>
> #define FUNCTION_INVARIANT(reg) \
> - static void get_##reg(struct kvm_vcpu *v, \
> + static u64 get_##reg(struct kvm_vcpu *v, \
> const struct sys_reg_desc *r) \
> { \
> ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \
> + return ((struct sys_reg_desc *)r)->val; \
> }
>
> FUNCTION_INVARIANT(midr_el1)
> FUNCTION_INVARIANT(revidr_el1)
> FUNCTION_INVARIANT(aidr_el1)
>
> -static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r)
> +static u64 get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r)
> {
> ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0);
> + return ((struct sys_reg_desc *)r)->val;
> }
>
> /* ->val is filled in by kvm_sys_reg_table_init() */
> diff --git a/arch/arm64/kvm/sys_regs.h b/arch/arm64/kvm/sys_regs.h
> index e88fd77309b2..21869319f6e1 100644
> --- a/arch/arm64/kvm/sys_regs.h
> +++ b/arch/arm64/kvm/sys_regs.h
> @@ -65,12 +65,12 @@ struct sys_reg_desc {
> const struct sys_reg_desc *);
>
> /* Initialization for vcpu. */
> - void (*reset)(struct kvm_vcpu *, const struct sys_reg_desc *);
> + u64 (*reset)(struct kvm_vcpu *, const struct sys_reg_desc *);
Could you add a comment what is return from reset() ?
Thank you,
Reiji
>
> /* Index into sys_reg[], or 0 if we don't need to save it. */
> int reg;
>
> - /* Value (usually reset value) */
> + /* Value (usually reset value), or write mask for idregs */
> u64 val;
>
> /* Custom get/set_user functions, fallback to generic if NULL */
> @@ -123,19 +123,21 @@ static inline bool read_zero(struct kvm_vcpu *vcpu,
> }
>
> /* Reset functions */
> -static inline void reset_unknown(struct kvm_vcpu *vcpu,
> +static inline u64 reset_unknown(struct kvm_vcpu *vcpu,
> const struct sys_reg_desc *r)
> {
> BUG_ON(!r->reg);
> BUG_ON(r->reg >= NR_SYS_REGS);
> __vcpu_sys_reg(vcpu, r->reg) = 0x1de7ec7edbadc0deULL;
> + return __vcpu_sys_reg(vcpu, r->reg);
> }
>
> -static inline void reset_val(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> +static inline u64 reset_val(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> {
> BUG_ON(!r->reg);
> BUG_ON(r->reg >= NR_SYS_REGS);
> __vcpu_sys_reg(vcpu, r->reg) = r->val;
> + return __vcpu_sys_reg(vcpu, r->reg);
> }
>
> static inline unsigned int sysreg_visibility(const struct kvm_vcpu *vcpu,
> --
> 2.40.0.348.gf938b09366-goog
>
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^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v6 5/6] KVM: arm64: Reuse fields of sys_reg_desc for idreg
2023-04-19 4:09 ` Reiji Watanabe
@ 2023-04-24 19:12 ` Jing Zhang
0 siblings, 0 replies; 18+ messages in thread
From: Jing Zhang @ 2023-04-24 19:12 UTC (permalink / raw)
To: Reiji Watanabe
Cc: KVM, KVMARM, ARMLinux, Marc Zyngier, Oliver Upton, Will Deacon,
Paolo Bonzini, James Morse, Alexandru Elisei, Suzuki K Poulose,
Fuad Tabba, Raghavendra Rao Ananta
Hi Reiji,
On Tue, Apr 18, 2023 at 9:09 PM Reiji Watanabe <reijiw@google.com> wrote:
>
> Hi Jing,
>
> On Tue, Apr 04, 2023 at 03:53:43AM +0000, Jing Zhang wrote:
> > Since reset() and val are not used for idreg in sys_reg_desc, they would
> > be used with other purposes for idregs.
> > The callback reset() would be used to return KVM sanitised id register
> > values. The u64 val would be used as mask for writable fields in idregs.
> > Only bits with 1 in val are writable from userspace.
> >
> > Signed-off-by: Jing Zhang <jingzhangos@google.com>
> > ---
> > arch/arm64/kvm/id_regs.c | 44 +++++++++++++++++++----------
> > arch/arm64/kvm/sys_regs.c | 59 +++++++++++++++++++++++++++------------
> > arch/arm64/kvm/sys_regs.h | 10 ++++---
> > 3 files changed, 77 insertions(+), 36 deletions(-)
> >
> > diff --git a/arch/arm64/kvm/id_regs.c b/arch/arm64/kvm/id_regs.c
> > index 6f65d30693fe..fe37b6786b4c 100644
> > --- a/arch/arm64/kvm/id_regs.c
> > +++ b/arch/arm64/kvm/id_regs.c
> > @@ -55,6 +55,11 @@ static u8 pmuver_to_perfmon(u8 pmuver)
> > }
> > }
> >
> > +static u64 general_read_kvm_sanitised_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd)
> > +{
> > + return read_sanitised_ftr_reg(reg_to_encoding(rd));
> > +}
> > +
> > u64 kvm_arm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id)
> > {
> > u64 val = IDREG(vcpu->kvm, id);
> > @@ -324,6 +329,17 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
> > return 0;
> > }
> >
> > +/*
> > + * Since reset() callback and field val are not used for idregs, they will be
> > + * used for specific purposes for idregs.
> > + * The reset() would return KVM sanitised register value. The value would be the
> > + * same as the host kernel sanitised value if there is no KVM sanitisation.
> > + * The val would be used as a mask indicating writable fields for the idreg.
> > + * Only bits with 1 are writable from userspace. This mask might not be
>
> Nit: This comment update seems to be in the next patch,
> since 'val' for AA64PFR0, AA64DFR0 and DFR0 is zero yet.
Even the val is all zero in this commit, but it is used the first time
here. I guess it is okay to have the comment here.
>
>
> > + * necessary in the future whenever all ID registers are enabled as writable
> > + * from userspace.
> > + */
> > +
> > /* sys_reg_desc initialiser for known cpufeature ID registers */
> > #define ID_SANITISED(name) { \
> > SYS_DESC(SYS_##name), \
> > @@ -331,6 +347,8 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
> > .get_user = get_id_reg, \
> > .set_user = set_id_reg, \
> > .visibility = id_visibility, \
> > + .reset = general_read_kvm_sanitised_reg,\
> > + .val = 0, \
> > }
> >
> > /* sys_reg_desc initialiser for known cpufeature ID registers */
> > @@ -340,6 +358,8 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
> > .get_user = get_id_reg, \
> > .set_user = set_id_reg, \
> > .visibility = aa32_id_visibility, \
> > + .reset = general_read_kvm_sanitised_reg,\
> > + .val = 0, \
> > }
> >
> > /*
> > @@ -352,7 +372,9 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
> > .access = access_id_reg, \
> > .get_user = get_id_reg, \
> > .set_user = set_id_reg, \
> > - .visibility = raz_visibility \
> > + .visibility = raz_visibility, \
> > + .reset = NULL, \
> > + .val = 0, \
> > }
> >
> > /*
> > @@ -366,6 +388,8 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
> > .get_user = get_id_reg, \
> > .set_user = set_id_reg, \
> > .visibility = raz_visibility, \
> > + .reset = NULL, \
> > + .val = 0, \
> > }
> >
> > const struct sys_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = {
> > @@ -476,10 +500,7 @@ int emulate_id_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params)
> > return 1;
> > }
> >
> > -/*
> > - * Set the guest's ID registers that are defined in id_reg_descs[]
> > - * with ID_SANITISED() to the host's sanitized value.
> > - */
> > +/* Initialize the guest's ID registers with KVM sanitised values. */
> > void kvm_arm_init_id_regs(struct kvm *kvm)
> > {
> > int i;
> > @@ -492,16 +513,11 @@ void kvm_arm_init_id_regs(struct kvm *kvm)
> > /* Shouldn't happen */
> > continue;
> >
> > - /*
> > - * Some hidden ID registers which are not in arm64_ftr_regs[]
> > - * would cause warnings from read_sanitised_ftr_reg().
> > - * Skip those ID registers to avoid the warnings.
> > - */
> > - if (id_reg_descs[i].visibility == raz_visibility)
> > - /* Hidden or reserved ID register */
> > - continue;
> > + val = 0;
> > + /* Read KVM sanitised register value if available */
> > + if (id_reg_descs[i].reset)
> > + val = id_reg_descs[i].reset(NULL, &id_reg_descs[i]);
> >
> > - val = read_sanitised_ftr_reg(id);
> > IDREG(kvm, id) = val;
> > }
> >
> > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> > index 15979c2b87ab..703cf833345a 100644
> > --- a/arch/arm64/kvm/sys_regs.c
> > +++ b/arch/arm64/kvm/sys_regs.c
> > @@ -540,10 +540,11 @@ static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
> > return 0;
> > }
> >
> > -static void reset_bvr(struct kvm_vcpu *vcpu,
> > +static u64 reset_bvr(struct kvm_vcpu *vcpu,
> > const struct sys_reg_desc *rd)
> > {
> > vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val;
> > + return rd->val;
> > }
> >
> > static bool trap_bcr(struct kvm_vcpu *vcpu,
> > @@ -576,10 +577,11 @@ static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
> > return 0;
> > }
> >
> > -static void reset_bcr(struct kvm_vcpu *vcpu,
> > +static u64 reset_bcr(struct kvm_vcpu *vcpu,
> > const struct sys_reg_desc *rd)
> > {
> > vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val;
> > + return rd->val;
> > }
> >
> > static bool trap_wvr(struct kvm_vcpu *vcpu,
> > @@ -613,10 +615,11 @@ static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
> > return 0;
> > }
> >
> > -static void reset_wvr(struct kvm_vcpu *vcpu,
> > +static u64 reset_wvr(struct kvm_vcpu *vcpu,
> > const struct sys_reg_desc *rd)
> > {
> > vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val;
> > + return rd->val;
> > }
> >
> > static bool trap_wcr(struct kvm_vcpu *vcpu,
> > @@ -649,25 +652,28 @@ static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
> > return 0;
> > }
> >
> > -static void reset_wcr(struct kvm_vcpu *vcpu,
> > +static u64 reset_wcr(struct kvm_vcpu *vcpu,
> > const struct sys_reg_desc *rd)
> > {
> > vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val;
> > + return rd->val;
> > }
> >
> > -static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> > +static u64 reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> > {
> > u64 amair = read_sysreg(amair_el1);
> > vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1);
> > + return amair;
> > }
> >
> > -static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> > +static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> > {
> > u64 actlr = read_sysreg(actlr_el1);
> > vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1);
> > + return actlr;
> > }
> >
> > -static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> > +static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> > {
> > u64 mpidr;
> >
> > @@ -681,7 +687,10 @@ static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> > mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
> > mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
> > mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
> > - vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1);
> > + mpidr |= (1ULL << 31);
> > + vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1);
> > +
> > + return mpidr;
> > }
> >
> > static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu,
> > @@ -693,13 +702,13 @@ static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu,
> > return REG_HIDDEN;
> > }
> >
> > -static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> > +static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> > {
> > u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX);
> >
> > /* No PMU available, any PMU reg may UNDEF... */
> > if (!kvm_arm_support_pmu_v3())
> > - return;
> > + return 0;
> >
> > n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT;
> > n &= ARMV8_PMU_PMCR_N_MASK;
> > @@ -708,33 +717,41 @@ static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> >
> > reset_unknown(vcpu, r);
> > __vcpu_sys_reg(vcpu, r->reg) &= mask;
> > +
> > + return __vcpu_sys_reg(vcpu, r->reg);
> > }
> >
> > -static void reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> > +static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> > {
> > reset_unknown(vcpu, r);
> > __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0);
> > +
> > + return __vcpu_sys_reg(vcpu, r->reg);
> > }
> >
> > -static void reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> > +static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> > {
> > reset_unknown(vcpu, r);
> > __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_EVTYPE_MASK;
> > +
> > + return __vcpu_sys_reg(vcpu, r->reg);
> > }
> >
> > -static void reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> > +static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> > {
> > reset_unknown(vcpu, r);
> > __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_COUNTER_MASK;
> > +
> > + return __vcpu_sys_reg(vcpu, r->reg);
> > }
> >
> > -static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> > +static u64 reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> > {
> > u64 pmcr;
> >
> > /* No PMU available, PMCR_EL0 may UNDEF... */
> > if (!kvm_arm_support_pmu_v3())
> > - return;
> > + return 0;
> >
> > /* Only preserve PMCR_EL0.N, and reset the rest to 0 */
> > pmcr = read_sysreg(pmcr_el0) & (ARMV8_PMU_PMCR_N_MASK << ARMV8_PMU_PMCR_N_SHIFT);
> > @@ -742,6 +759,8 @@ static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> > pmcr |= ARMV8_PMU_PMCR_LC;
> >
> > __vcpu_sys_reg(vcpu, r->reg) = pmcr;
> > +
> > + return __vcpu_sys_reg(vcpu, r->reg);
> > }
> >
> > static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
> > @@ -1221,7 +1240,7 @@ static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
> > * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary
> > * by the physical CPU which the vcpu currently resides in.
> > */
> > -static void reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> > +static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> > {
> > u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0);
> > u64 clidr;
> > @@ -1269,6 +1288,8 @@ static void reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> > clidr |= 2 << CLIDR_TTYPE_SHIFT(loc);
> >
> > __vcpu_sys_reg(vcpu, r->reg) = clidr;
> > +
> > + return __vcpu_sys_reg(vcpu, r->reg);
> > }
> >
> > static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
> > @@ -2622,19 +2643,21 @@ id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id,
> > */
> >
> > #define FUNCTION_INVARIANT(reg) \
> > - static void get_##reg(struct kvm_vcpu *v, \
> > + static u64 get_##reg(struct kvm_vcpu *v, \
> > const struct sys_reg_desc *r) \
> > { \
> > ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \
> > + return ((struct sys_reg_desc *)r)->val; \
> > }
> >
> > FUNCTION_INVARIANT(midr_el1)
> > FUNCTION_INVARIANT(revidr_el1)
> > FUNCTION_INVARIANT(aidr_el1)
> >
> > -static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r)
> > +static u64 get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r)
> > {
> > ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0);
> > + return ((struct sys_reg_desc *)r)->val;
> > }
> >
> > /* ->val is filled in by kvm_sys_reg_table_init() */
> > diff --git a/arch/arm64/kvm/sys_regs.h b/arch/arm64/kvm/sys_regs.h
> > index e88fd77309b2..21869319f6e1 100644
> > --- a/arch/arm64/kvm/sys_regs.h
> > +++ b/arch/arm64/kvm/sys_regs.h
> > @@ -65,12 +65,12 @@ struct sys_reg_desc {
> > const struct sys_reg_desc *);
> >
> > /* Initialization for vcpu. */
> > - void (*reset)(struct kvm_vcpu *, const struct sys_reg_desc *);
> > + u64 (*reset)(struct kvm_vcpu *, const struct sys_reg_desc *);
>
> Could you add a comment what is return from reset() ?
The returned value for idregs is described both in the commit message
and the comment block in previous change.
>
> Thank you,
> Reiji
>
> >
> > /* Index into sys_reg[], or 0 if we don't need to save it. */
> > int reg;
> >
> > - /* Value (usually reset value) */
> > + /* Value (usually reset value), or write mask for idregs */
> > u64 val;
> >
> > /* Custom get/set_user functions, fallback to generic if NULL */
> > @@ -123,19 +123,21 @@ static inline bool read_zero(struct kvm_vcpu *vcpu,
> > }
> >
> > /* Reset functions */
> > -static inline void reset_unknown(struct kvm_vcpu *vcpu,
> > +static inline u64 reset_unknown(struct kvm_vcpu *vcpu,
> > const struct sys_reg_desc *r)
> > {
> > BUG_ON(!r->reg);
> > BUG_ON(r->reg >= NR_SYS_REGS);
> > __vcpu_sys_reg(vcpu, r->reg) = 0x1de7ec7edbadc0deULL;
> > + return __vcpu_sys_reg(vcpu, r->reg);
> > }
> >
> > -static inline void reset_val(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> > +static inline u64 reset_val(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> > {
> > BUG_ON(!r->reg);
> > BUG_ON(r->reg >= NR_SYS_REGS);
> > __vcpu_sys_reg(vcpu, r->reg) = r->val;
> > + return __vcpu_sys_reg(vcpu, r->reg);
> > }
> >
> > static inline unsigned int sysreg_visibility(const struct kvm_vcpu *vcpu,
> > --
> > 2.40.0.348.gf938b09366-goog
> >
Thanks,
Jing
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v6 6/6] KVM: arm64: Refactor writings for PMUVer/CSV2/CSV3
2023-04-04 3:53 [PATCH v6 0/6] Support writable CPU ID registers from userspace Jing Zhang
` (4 preceding siblings ...)
2023-04-04 3:53 ` [PATCH v6 5/6] KVM: arm64: Reuse fields of sys_reg_desc for idreg Jing Zhang
@ 2023-04-04 3:53 ` Jing Zhang
2023-04-19 4:59 ` Reiji Watanabe
5 siblings, 1 reply; 18+ messages in thread
From: Jing Zhang @ 2023-04-04 3:53 UTC (permalink / raw)
To: KVM, KVMARM, ARMLinux, Marc Zyngier, Oliver Upton
Cc: Will Deacon, Paolo Bonzini, James Morse, Alexandru Elisei,
Suzuki K Poulose, Fuad Tabba, Reiji Watanabe,
Raghavendra Rao Ananta, Jing Zhang
Refactor writings for ID_AA64PFR0_EL1.[CSV2|CSV3],
ID_AA64DFR0_EL1.PMUVer and ID_DFR0_ELF.PerfMon based on utilities
introduced by ID register descriptor array.
Signed-off-by: Jing Zhang <jingzhangos@google.com>
---
arch/arm64/include/asm/cpufeature.h | 1 +
arch/arm64/kernel/cpufeature.c | 2 +-
arch/arm64/kvm/id_regs.c | 284 ++++++++++++++++++++--------
3 files changed, 203 insertions(+), 84 deletions(-)
diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index 6bf013fb110d..dc769c2eb7a4 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -915,6 +915,7 @@ static inline unsigned int get_vmid_bits(u64 mmfr1)
return 8;
}
+s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, s64 cur);
struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id);
extern struct arm64_ftr_override id_aa64mmfr1_override;
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 2e3e55139777..677ec4fe9f6b 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -791,7 +791,7 @@ static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
return reg;
}
-static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
+s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
s64 cur)
{
s64 ret = 0;
diff --git a/arch/arm64/kvm/id_regs.c b/arch/arm64/kvm/id_regs.c
index fe37b6786b4c..33968ada29bb 100644
--- a/arch/arm64/kvm/id_regs.c
+++ b/arch/arm64/kvm/id_regs.c
@@ -18,6 +18,66 @@
#include "sys_regs.h"
+/**
+ * arm64_check_features() - Check if a feature register value constitutes
+ * a subset of features indicated by the idreg's KVM sanitised limit.
+ *
+ * This function will check if each feature field of @val is the "safe" value
+ * against idreg's KVM sanitised limit return from reset() callback.
+ * If a field value in @val is the same as the one in limit, it is always
+ * considered the safe value regardless For register fields that are not in
+ * writable, only the value in limit is considered the safe value.
+ *
+ * Return: 0 if all the fields are safe. Otherwise, return negative errno.
+ */
+static int arm64_check_features(struct kvm_vcpu *vcpu,
+ const struct sys_reg_desc *rd,
+ u64 val)
+{
+ const struct arm64_ftr_reg *ftr_reg;
+ const struct arm64_ftr_bits *ftrp = NULL;
+ u32 id = reg_to_encoding(rd);
+ u64 writable_mask = rd->val;
+ u64 limit = 0;
+ u64 mask = 0;
+
+ /* For hidden and unallocated idregs without reset, only val = 0 is allowed. */
+ if (rd->reset) {
+ limit = rd->reset(vcpu, rd);
+ ftr_reg = get_arm64_ftr_reg(id);
+ if (!ftr_reg)
+ return -EINVAL;
+ ftrp = ftr_reg->ftr_bits;
+ }
+
+ for (; ftrp && ftrp->width; ftrp++) {
+ s64 f_val, f_lim, safe_val;
+ u64 ftr_mask;
+
+ ftr_mask = arm64_ftr_mask(ftrp);
+ if ((ftr_mask & writable_mask) != ftr_mask)
+ continue;
+
+ f_val = arm64_ftr_value(ftrp, val);
+ f_lim = arm64_ftr_value(ftrp, limit);
+ mask |= ftr_mask;
+
+ if (f_val == f_lim)
+ safe_val = f_val;
+ else
+ safe_val = arm64_ftr_safe_value(ftrp, f_val, f_lim);
+
+ if (safe_val != f_val)
+ return -E2BIG;
+ }
+
+ /* For fields that are not writable, values in limit are the safe values. */
+ if ((val & ~mask) != (limit & ~mask))
+ return -E2BIG;
+
+ return 0;
+}
+
static u8 vcpu_pmuver(const struct kvm_vcpu *vcpu)
{
if (kvm_vcpu_has_pmu(vcpu))
@@ -68,7 +128,6 @@ u64 kvm_arm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id)
case SYS_ID_AA64PFR0_EL1:
if (!vcpu_has_sve(vcpu))
val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE);
- val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU);
if (kvm_vgic_global_state.type == VGIC_V3) {
val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC);
val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC), 1);
@@ -95,15 +154,10 @@ u64 kvm_arm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id)
val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT);
break;
case SYS_ID_AA64DFR0_EL1:
- /* Limit debug to ARMv8.0 */
- val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer);
- val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), 6);
/* Set PMUver to the required version */
val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer),
vcpu_pmuver(vcpu));
- /* Hide SPE from guests */
- val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer);
break;
case SYS_ID_DFR0_EL1:
val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon);
@@ -162,9 +216,14 @@ static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
u64 val)
{
- /* This is what we mean by invariant: you can't change it. */
- if (val != read_id_reg(vcpu, rd))
- return -EINVAL;
+ u32 id = reg_to_encoding(rd);
+ int ret;
+
+ ret = arm64_check_features(vcpu, rd, val);
+ if (ret)
+ return ret;
+
+ IDREG(vcpu->kvm, id) = val;
return 0;
}
@@ -198,12 +257,40 @@ static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu,
return id_visibility(vcpu, r);
}
+static u64 read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
+ const struct sys_reg_desc *rd)
+{
+ u64 val;
+ u32 id = reg_to_encoding(rd);
+
+ val = read_sanitised_ftr_reg(id);
+ /*
+ * The default is to expose CSV2 == 1 if the HW isn't affected.
+ * Although this is a per-CPU feature, we make it global because
+ * asymmetric systems are just a nuisance.
+ *
+ * Userspace can override this as long as it doesn't promise
+ * the impossible.
+ */
+ if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) {
+ val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2);
+ val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2), 1);
+ }
+ if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) {
+ val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3);
+ val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3), 1);
+ }
+
+ val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU);
+
+ return val;
+}
+
static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
const struct sys_reg_desc *rd,
u64 val)
{
u8 csv2, csv3;
- u64 sval = val;
/*
* Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as
@@ -219,16 +306,30 @@ static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
if (csv3 > 1 || (csv3 && arm64_get_meltdown_state() != SPECTRE_UNAFFECTED))
return -EINVAL;
- /* We can only differ with CSV[23], and anything else is an error */
- val ^= read_id_reg(vcpu, rd);
- val &= ~(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2) |
- ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3));
- if (val)
- return -EINVAL;
+ return set_id_reg(vcpu, rd, val);
+}
+
+static u64 read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
+ const struct sys_reg_desc *rd)
+{
+ u64 val;
+ u32 id = reg_to_encoding(rd);
- IDREG(vcpu->kvm, reg_to_encoding(rd)) = sval;
+ val = read_sanitised_ftr_reg(id);
+ /* Limit debug to ARMv8.0 */
+ val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer);
+ val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), 6);
+ /*
+ * Initialise the default PMUver before there is a chance to
+ * create an actual PMU.
+ */
+ val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
+ val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer),
+ kvm_arm_pmu_get_pmuver_limit());
+ /* Hide SPE from guests */
+ val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer);
- return 0;
+ return val;
}
static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
@@ -237,6 +338,7 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
{
u8 pmuver, host_pmuver;
bool valid_pmu;
+ int ret;
host_pmuver = kvm_arm_pmu_get_pmuver_limit();
@@ -256,36 +358,61 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
if (kvm_vcpu_has_pmu(vcpu) != valid_pmu)
return -EINVAL;
- /* We can only differ with PMUver, and anything else is an error */
- val ^= read_id_reg(vcpu, rd);
- val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
- if (val)
- return -EINVAL;
+ if (!valid_pmu) {
+ /*
+ * Ignore the PMUVer filed in @val. The PMUVer would be determined
+ * by arch flags bit KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU,
+ */
+ pmuver = FIELD_GET(ID_AA64DFR0_EL1_PMUVer_MASK, read_id_reg(vcpu, rd));
+ val &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
+ val |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK, pmuver);
+ }
- if (valid_pmu) {
- mutex_lock(&vcpu->kvm->arch.config_lock);
- IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
- IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK,
- pmuver);
+ mutex_lock(&vcpu->kvm->arch.config_lock);
- IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &= ~ID_DFR0_EL1_PerfMon_MASK;
- IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK,
- pmuver_to_perfmon(pmuver));
+ ret = set_id_reg(vcpu, rd, val);
+ if (ret) {
mutex_unlock(&vcpu->kvm->arch.config_lock);
- } else {
+ return ret;
+ }
+
+ IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &= ~ID_DFR0_EL1_PerfMon_MASK;
+ IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK,
+ pmuver_to_perfmon(pmuver));
+
+ if (!valid_pmu)
assign_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags,
pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF);
- }
+
+ mutex_unlock(&vcpu->kvm->arch.config_lock);
return 0;
}
+static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu,
+ const struct sys_reg_desc *rd)
+{
+ u64 val;
+ u32 id = reg_to_encoding(rd);
+
+ val = read_sanitised_ftr_reg(id);
+ /*
+ * Initialise the default PMUver before there is a chance to
+ * create an actual PMU.
+ */
+ val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon);
+ val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), kvm_arm_pmu_get_pmuver_limit());
+
+ return val;
+}
+
static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
const struct sys_reg_desc *rd,
u64 val)
{
u8 perfmon, host_perfmon;
bool valid_pmu;
+ int ret;
host_perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit());
@@ -306,25 +433,33 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
if (kvm_vcpu_has_pmu(vcpu) != valid_pmu)
return -EINVAL;
- /* We can only differ with PerfMon, and anything else is an error */
- val ^= read_id_reg(vcpu, rd);
- val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon);
- if (val)
- return -EINVAL;
+ if (!valid_pmu) {
+ /*
+ * Ignore the PerfMon filed in @val. The PerfMon would be determined
+ * by arch flags bit KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU,
+ */
+ perfmon = FIELD_GET(ID_DFR0_EL1_PerfMon_MASK, read_id_reg(vcpu, rd));
+ val &= ~ID_DFR0_EL1_PerfMon_MASK;
+ val |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK, perfmon);
+ }
- if (valid_pmu) {
- mutex_lock(&vcpu->kvm->arch.config_lock);
- IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &= ~ID_DFR0_EL1_PerfMon_MASK;
- IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK, perfmon);
+ mutex_lock(&vcpu->kvm->arch.config_lock);
- IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
- IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK,
- perfmon_to_pmuver(perfmon));
+ ret = set_id_reg(vcpu, rd, val);
+ if (ret) {
mutex_unlock(&vcpu->kvm->arch.config_lock);
- } else {
+ return ret;
+ }
+
+ IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
+ IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK,
+ perfmon_to_pmuver(perfmon));
+
+ if (!valid_pmu)
assign_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags,
perfmon == ID_DFR0_EL1_PerfMon_IMPDEF);
- }
+
+ mutex_unlock(&vcpu->kvm->arch.config_lock);
return 0;
}
@@ -402,9 +537,13 @@ const struct sys_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = {
/* CRm=1 */
AA32_ID_SANITISED(ID_PFR0_EL1),
AA32_ID_SANITISED(ID_PFR1_EL1),
- { SYS_DESC(SYS_ID_DFR0_EL1), .access = access_id_reg,
- .get_user = get_id_reg, .set_user = set_id_dfr0_el1,
- .visibility = aa32_id_visibility, },
+ { SYS_DESC(SYS_ID_DFR0_EL1),
+ .access = access_id_reg,
+ .get_user = get_id_reg,
+ .set_user = set_id_dfr0_el1,
+ .visibility = aa32_id_visibility,
+ .reset = read_sanitised_id_dfr0_el1,
+ .val = ID_DFR0_EL1_PerfMon_MASK, },
ID_HIDDEN(ID_AFR0_EL1),
AA32_ID_SANITISED(ID_MMFR0_EL1),
AA32_ID_SANITISED(ID_MMFR1_EL1),
@@ -433,8 +572,12 @@ const struct sys_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = {
/* AArch64 ID registers */
/* CRm=4 */
- { SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg,
- .get_user = get_id_reg, .set_user = set_id_aa64pfr0_el1, },
+ { SYS_DESC(SYS_ID_AA64PFR0_EL1),
+ .access = access_id_reg,
+ .get_user = get_id_reg,
+ .set_user = set_id_aa64pfr0_el1,
+ .reset = read_sanitised_id_aa64pfr0_el1,
+ .val = ID_AA64PFR0_EL1_CSV2_MASK | ID_AA64PFR0_EL1_CSV3_MASK, },
ID_SANITISED(ID_AA64PFR1_EL1),
ID_UNALLOCATED(4, 2),
ID_UNALLOCATED(4, 3),
@@ -444,8 +587,12 @@ const struct sys_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = {
ID_UNALLOCATED(4, 7),
/* CRm=5 */
- { SYS_DESC(SYS_ID_AA64DFR0_EL1), .access = access_id_reg,
- .get_user = get_id_reg, .set_user = set_id_aa64dfr0_el1, },
+ { SYS_DESC(SYS_ID_AA64DFR0_EL1),
+ .access = access_id_reg,
+ .get_user = get_id_reg,
+ .set_user = set_id_aa64dfr0_el1,
+ .reset = read_sanitised_id_aa64dfr0_el1,
+ .val = ID_AA64DFR0_EL1_PMUVer_MASK, },
ID_SANITISED(ID_AA64DFR1_EL1),
ID_UNALLOCATED(5, 2),
ID_UNALLOCATED(5, 3),
@@ -520,33 +667,4 @@ void kvm_arm_init_id_regs(struct kvm *kvm)
IDREG(kvm, id) = val;
}
-
- /*
- * The default is to expose CSV2 == 1 if the HW isn't affected.
- * Although this is a per-CPU feature, we make it global because
- * asymmetric systems are just a nuisance.
- *
- * Userspace can override this as long as it doesn't promise
- * the impossible.
- */
- val = IDREG(kvm, SYS_ID_AA64PFR0_EL1);
-
- if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) {
- val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2);
- val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2), 1);
- }
- if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) {
- val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3);
- val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3), 1);
- }
-
- IDREG(kvm, SYS_ID_AA64PFR0_EL1) = val;
-
- /*
- * Initialise the default PMUver before there is a chance to
- * create an actual PMU.
- */
- IDREG(kvm, SYS_ID_AA64DFR0_EL1) &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
- IDREG(kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer),
- kvm_arm_pmu_get_pmuver_limit());
}
--
2.40.0.348.gf938b09366-goog
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^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v6 6/6] KVM: arm64: Refactor writings for PMUVer/CSV2/CSV3
2023-04-04 3:53 ` [PATCH v6 6/6] KVM: arm64: Refactor writings for PMUVer/CSV2/CSV3 Jing Zhang
@ 2023-04-19 4:59 ` Reiji Watanabe
2023-04-24 19:19 ` Jing Zhang
0 siblings, 1 reply; 18+ messages in thread
From: Reiji Watanabe @ 2023-04-19 4:59 UTC (permalink / raw)
To: Jing Zhang
Cc: KVM, KVMARM, ARMLinux, Marc Zyngier, Oliver Upton, Will Deacon,
Paolo Bonzini, James Morse, Alexandru Elisei, Suzuki K Poulose,
Fuad Tabba, Raghavendra Rao Ananta
Hi Jing,
On Tue, Apr 04, 2023 at 03:53:44AM +0000, Jing Zhang wrote:
> Refactor writings for ID_AA64PFR0_EL1.[CSV2|CSV3],
> ID_AA64DFR0_EL1.PMUVer and ID_DFR0_ELF.PerfMon based on utilities
> introduced by ID register descriptor array.
>
> Signed-off-by: Jing Zhang <jingzhangos@google.com>
> ---
> arch/arm64/include/asm/cpufeature.h | 1 +
> arch/arm64/kernel/cpufeature.c | 2 +-
> arch/arm64/kvm/id_regs.c | 284 ++++++++++++++++++++--------
> 3 files changed, 203 insertions(+), 84 deletions(-)
>
> diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
> index 6bf013fb110d..dc769c2eb7a4 100644
> --- a/arch/arm64/include/asm/cpufeature.h
> +++ b/arch/arm64/include/asm/cpufeature.h
> @@ -915,6 +915,7 @@ static inline unsigned int get_vmid_bits(u64 mmfr1)
> return 8;
> }
>
> +s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, s64 cur);
> struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id);
>
> extern struct arm64_ftr_override id_aa64mmfr1_override;
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 2e3e55139777..677ec4fe9f6b 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -791,7 +791,7 @@ static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
> return reg;
> }
>
> -static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
> +s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
> s64 cur)
> {
> s64 ret = 0;
> diff --git a/arch/arm64/kvm/id_regs.c b/arch/arm64/kvm/id_regs.c
> index fe37b6786b4c..33968ada29bb 100644
> --- a/arch/arm64/kvm/id_regs.c
> +++ b/arch/arm64/kvm/id_regs.c
> @@ -18,6 +18,66 @@
>
> #include "sys_regs.h"
>
> +/**
> + * arm64_check_features() - Check if a feature register value constitutes
> + * a subset of features indicated by the idreg's KVM sanitised limit.
> + *
> + * This function will check if each feature field of @val is the "safe" value
> + * against idreg's KVM sanitised limit return from reset() callback.
> + * If a field value in @val is the same as the one in limit, it is always
> + * considered the safe value regardless For register fields that are not in
> + * writable, only the value in limit is considered the safe value.
> + *
> + * Return: 0 if all the fields are safe. Otherwise, return negative errno.
> + */
> +static int arm64_check_features(struct kvm_vcpu *vcpu,
> + const struct sys_reg_desc *rd,
> + u64 val)
> +{
> + const struct arm64_ftr_reg *ftr_reg;
> + const struct arm64_ftr_bits *ftrp = NULL;
> + u32 id = reg_to_encoding(rd);
> + u64 writable_mask = rd->val;
> + u64 limit = 0;
> + u64 mask = 0;
> +
> + /* For hidden and unallocated idregs without reset, only val = 0 is allowed. */
> + if (rd->reset) {
> + limit = rd->reset(vcpu, rd);
> + ftr_reg = get_arm64_ftr_reg(id);
> + if (!ftr_reg)
> + return -EINVAL;
> + ftrp = ftr_reg->ftr_bits;
> + }
> +
> + for (; ftrp && ftrp->width; ftrp++) {
> + s64 f_val, f_lim, safe_val;
> + u64 ftr_mask;
> +
> + ftr_mask = arm64_ftr_mask(ftrp);
> + if ((ftr_mask & writable_mask) != ftr_mask)
> + continue;
> +
> + f_val = arm64_ftr_value(ftrp, val);
> + f_lim = arm64_ftr_value(ftrp, limit);
> + mask |= ftr_mask;
> +
> + if (f_val == f_lim)
> + safe_val = f_val;
> + else
> + safe_val = arm64_ftr_safe_value(ftrp, f_val, f_lim);
Since PMUVer and PerfMon is defined as FTR_EXACT, I believe having lower
value in those two fields than the limit always ends up getting -E2BIG.
Or am I missing something ??
FYI. IIRC, we have some more fields in other ID registers that KVM
shouldn't use as is.
> +
> + if (safe_val != f_val)
> + return -E2BIG;
> + }
> +
> + /* For fields that are not writable, values in limit are the safe values. */
> + if ((val & ~mask) != (limit & ~mask))
> + return -E2BIG;
> +
> + return 0;
> +}
> +
> static u8 vcpu_pmuver(const struct kvm_vcpu *vcpu)
> {
> if (kvm_vcpu_has_pmu(vcpu))
> @@ -68,7 +128,6 @@ u64 kvm_arm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id)
> case SYS_ID_AA64PFR0_EL1:
> if (!vcpu_has_sve(vcpu))
> val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE);
> - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU);
> if (kvm_vgic_global_state.type == VGIC_V3) {
> val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC);
> val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC), 1);
> @@ -95,15 +154,10 @@ u64 kvm_arm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id)
> val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT);
> break;
> case SYS_ID_AA64DFR0_EL1:
> - /* Limit debug to ARMv8.0 */
> - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer);
> - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), 6);
> /* Set PMUver to the required version */
> val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
> val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer),
> vcpu_pmuver(vcpu));
> - /* Hide SPE from guests */
> - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer);
> break;
> case SYS_ID_DFR0_EL1:
> val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon);
> @@ -162,9 +216,14 @@ static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
> static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
> u64 val)
> {
> - /* This is what we mean by invariant: you can't change it. */
> - if (val != read_id_reg(vcpu, rd))
> - return -EINVAL;
> + u32 id = reg_to_encoding(rd);
> + int ret;
> +
> + ret = arm64_check_features(vcpu, rd, val);
> + if (ret)
> + return ret;
> +
> + IDREG(vcpu->kvm, id) = val;
>
> return 0;
> }
> @@ -198,12 +257,40 @@ static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu,
> return id_visibility(vcpu, r);
> }
>
> +static u64 read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
> + const struct sys_reg_desc *rd)
> +{
> + u64 val;
> + u32 id = reg_to_encoding(rd);
> +
> + val = read_sanitised_ftr_reg(id);
> + /*
> + * The default is to expose CSV2 == 1 if the HW isn't affected.
> + * Although this is a per-CPU feature, we make it global because
> + * asymmetric systems are just a nuisance.
> + *
> + * Userspace can override this as long as it doesn't promise
> + * the impossible.
> + */
> + if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) {
> + val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2);
> + val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2), 1);
> + }
> + if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) {
> + val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3);
> + val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3), 1);
> + }
> +
> + val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU);
> +
> + return val;
> +}
> +
> static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
> const struct sys_reg_desc *rd,
> u64 val)
> {
> u8 csv2, csv3;
> - u64 sval = val;
>
> /*
> * Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as
> @@ -219,16 +306,30 @@ static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
> if (csv3 > 1 || (csv3 && arm64_get_meltdown_state() != SPECTRE_UNAFFECTED))
> return -EINVAL;
>
> - /* We can only differ with CSV[23], and anything else is an error */
> - val ^= read_id_reg(vcpu, rd);
> - val &= ~(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2) |
> - ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3));
> - if (val)
> - return -EINVAL;
> + return set_id_reg(vcpu, rd, val);
> +}
> +
> +static u64 read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
> + const struct sys_reg_desc *rd)
> +{
> + u64 val;
> + u32 id = reg_to_encoding(rd);
>
> - IDREG(vcpu->kvm, reg_to_encoding(rd)) = sval;
> + val = read_sanitised_ftr_reg(id);
> + /* Limit debug to ARMv8.0 */
> + val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer);
> + val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), 6);
> + /*
> + * Initialise the default PMUver before there is a chance to
> + * create an actual PMU.
> + */
> + val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
> + val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer),
> + kvm_arm_pmu_get_pmuver_limit());
> + /* Hide SPE from guests */
> + val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer);
>
> - return 0;
> + return val;
> }
>
> static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
> @@ -237,6 +338,7 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
> {
> u8 pmuver, host_pmuver;
> bool valid_pmu;
> + int ret;
>
> host_pmuver = kvm_arm_pmu_get_pmuver_limit();
>
> @@ -256,36 +358,61 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
> if (kvm_vcpu_has_pmu(vcpu) != valid_pmu)
> return -EINVAL;
>
> - /* We can only differ with PMUver, and anything else is an error */
> - val ^= read_id_reg(vcpu, rd);
> - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
> - if (val)
> - return -EINVAL;
> + if (!valid_pmu) {
> + /*
> + * Ignore the PMUVer filed in @val. The PMUVer would be determined
> + * by arch flags bit KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU,
> + */
> + pmuver = FIELD_GET(ID_AA64DFR0_EL1_PMUVer_MASK, read_id_reg(vcpu, rd));
As vPMU is not configured for this vCPU, I believe pmuver will be
0x0 or 0xf. I think that is not what we want there.
Or am I missing something ?
> + val &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
> + val |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK, pmuver);
> + }
>
> - if (valid_pmu) {
> - mutex_lock(&vcpu->kvm->arch.config_lock);
> - IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
> - IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK,
> - pmuver);
> + mutex_lock(&vcpu->kvm->arch.config_lock);
>
> - IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &= ~ID_DFR0_EL1_PerfMon_MASK;
> - IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK,
> - pmuver_to_perfmon(pmuver));
> + ret = set_id_reg(vcpu, rd, val);
> + if (ret) {
> mutex_unlock(&vcpu->kvm->arch.config_lock);
> - } else {
> + return ret;
> + }
> +
> + IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &= ~ID_DFR0_EL1_PerfMon_MASK;
> + IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK,
> + pmuver_to_perfmon(pmuver));
> +
> + if (!valid_pmu)
> assign_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags,
> pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF);
> - }
> +
> + mutex_unlock(&vcpu->kvm->arch.config_lock);
>
> return 0;
> }
>
> +static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu,
> + const struct sys_reg_desc *rd)
> +{
> + u64 val;
> + u32 id = reg_to_encoding(rd);
> +
> + val = read_sanitised_ftr_reg(id);
> + /*
> + * Initialise the default PMUver before there is a chance to
> + * create an actual PMU.
> + */
> + val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon);
> + val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), kvm_arm_pmu_get_pmuver_limit());
> +
> + return val;
> +}
> +
> static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
> const struct sys_reg_desc *rd,
> u64 val)
> {
> u8 perfmon, host_perfmon;
> bool valid_pmu;
> + int ret;
>
> host_perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit());
>
> @@ -306,25 +433,33 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
> if (kvm_vcpu_has_pmu(vcpu) != valid_pmu)
> return -EINVAL;
>
> - /* We can only differ with PerfMon, and anything else is an error */
> - val ^= read_id_reg(vcpu, rd);
> - val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon);
> - if (val)
> - return -EINVAL;
> + if (!valid_pmu) {
> + /*
> + * Ignore the PerfMon filed in @val. The PerfMon would be determined
> + * by arch flags bit KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU,
> + */
I have the same comment as set_id_aa64dfr0_el1().
Thank you,
Reiji
> + perfmon = FIELD_GET(ID_DFR0_EL1_PerfMon_MASK, read_id_reg(vcpu, rd));
> + val &= ~ID_DFR0_EL1_PerfMon_MASK;
> + val |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK, perfmon);
> + }
>
> - if (valid_pmu) {
> - mutex_lock(&vcpu->kvm->arch.config_lock);
> - IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &= ~ID_DFR0_EL1_PerfMon_MASK;
> - IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK, perfmon);
> + mutex_lock(&vcpu->kvm->arch.config_lock);
>
> - IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
> - IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK,
> - perfmon_to_pmuver(perfmon));
> + ret = set_id_reg(vcpu, rd, val);
> + if (ret) {
> mutex_unlock(&vcpu->kvm->arch.config_lock);
> - } else {
> + return ret;
> + }
> +
> + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
> + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK,
> + perfmon_to_pmuver(perfmon));
> +
> + if (!valid_pmu)
> assign_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags,
> perfmon == ID_DFR0_EL1_PerfMon_IMPDEF);
> - }
> +
> + mutex_unlock(&vcpu->kvm->arch.config_lock);
>
> return 0;
> }
> @@ -402,9 +537,13 @@ const struct sys_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = {
> /* CRm=1 */
> AA32_ID_SANITISED(ID_PFR0_EL1),
> AA32_ID_SANITISED(ID_PFR1_EL1),
> - { SYS_DESC(SYS_ID_DFR0_EL1), .access = access_id_reg,
> - .get_user = get_id_reg, .set_user = set_id_dfr0_el1,
> - .visibility = aa32_id_visibility, },
> + { SYS_DESC(SYS_ID_DFR0_EL1),
> + .access = access_id_reg,
> + .get_user = get_id_reg,
> + .set_user = set_id_dfr0_el1,
> + .visibility = aa32_id_visibility,
> + .reset = read_sanitised_id_dfr0_el1,
> + .val = ID_DFR0_EL1_PerfMon_MASK, },
> ID_HIDDEN(ID_AFR0_EL1),
> AA32_ID_SANITISED(ID_MMFR0_EL1),
> AA32_ID_SANITISED(ID_MMFR1_EL1),
> @@ -433,8 +572,12 @@ const struct sys_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = {
>
> /* AArch64 ID registers */
> /* CRm=4 */
> - { SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg,
> - .get_user = get_id_reg, .set_user = set_id_aa64pfr0_el1, },
> + { SYS_DESC(SYS_ID_AA64PFR0_EL1),
> + .access = access_id_reg,
> + .get_user = get_id_reg,
> + .set_user = set_id_aa64pfr0_el1,
> + .reset = read_sanitised_id_aa64pfr0_el1,
> + .val = ID_AA64PFR0_EL1_CSV2_MASK | ID_AA64PFR0_EL1_CSV3_MASK, },
> ID_SANITISED(ID_AA64PFR1_EL1),
> ID_UNALLOCATED(4, 2),
> ID_UNALLOCATED(4, 3),
> @@ -444,8 +587,12 @@ const struct sys_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = {
> ID_UNALLOCATED(4, 7),
>
> /* CRm=5 */
> - { SYS_DESC(SYS_ID_AA64DFR0_EL1), .access = access_id_reg,
> - .get_user = get_id_reg, .set_user = set_id_aa64dfr0_el1, },
> + { SYS_DESC(SYS_ID_AA64DFR0_EL1),
> + .access = access_id_reg,
> + .get_user = get_id_reg,
> + .set_user = set_id_aa64dfr0_el1,
> + .reset = read_sanitised_id_aa64dfr0_el1,
> + .val = ID_AA64DFR0_EL1_PMUVer_MASK, },
> ID_SANITISED(ID_AA64DFR1_EL1),
> ID_UNALLOCATED(5, 2),
> ID_UNALLOCATED(5, 3),
> @@ -520,33 +667,4 @@ void kvm_arm_init_id_regs(struct kvm *kvm)
>
> IDREG(kvm, id) = val;
> }
> -
> - /*
> - * The default is to expose CSV2 == 1 if the HW isn't affected.
> - * Although this is a per-CPU feature, we make it global because
> - * asymmetric systems are just a nuisance.
> - *
> - * Userspace can override this as long as it doesn't promise
> - * the impossible.
> - */
> - val = IDREG(kvm, SYS_ID_AA64PFR0_EL1);
> -
> - if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) {
> - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2);
> - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2), 1);
> - }
> - if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) {
> - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3);
> - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3), 1);
> - }
> -
> - IDREG(kvm, SYS_ID_AA64PFR0_EL1) = val;
> -
> - /*
> - * Initialise the default PMUver before there is a chance to
> - * create an actual PMU.
> - */
> - IDREG(kvm, SYS_ID_AA64DFR0_EL1) &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
> - IDREG(kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer),
> - kvm_arm_pmu_get_pmuver_limit());
> }
> --
> 2.40.0.348.gf938b09366-goog
>
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^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v6 6/6] KVM: arm64: Refactor writings for PMUVer/CSV2/CSV3
2023-04-19 4:59 ` Reiji Watanabe
@ 2023-04-24 19:19 ` Jing Zhang
2023-04-25 2:19 ` Reiji Watanabe
0 siblings, 1 reply; 18+ messages in thread
From: Jing Zhang @ 2023-04-24 19:19 UTC (permalink / raw)
To: Reiji Watanabe
Cc: KVM, KVMARM, ARMLinux, Marc Zyngier, Oliver Upton, Will Deacon,
Paolo Bonzini, James Morse, Alexandru Elisei, Suzuki K Poulose,
Fuad Tabba, Raghavendra Rao Ananta
Hi Reiji,
On Tue, Apr 18, 2023 at 9:59 PM Reiji Watanabe <reijiw@google.com> wrote:
>
> Hi Jing,
>
> On Tue, Apr 04, 2023 at 03:53:44AM +0000, Jing Zhang wrote:
> > Refactor writings for ID_AA64PFR0_EL1.[CSV2|CSV3],
> > ID_AA64DFR0_EL1.PMUVer and ID_DFR0_ELF.PerfMon based on utilities
> > introduced by ID register descriptor array.
> >
> > Signed-off-by: Jing Zhang <jingzhangos@google.com>
> > ---
> > arch/arm64/include/asm/cpufeature.h | 1 +
> > arch/arm64/kernel/cpufeature.c | 2 +-
> > arch/arm64/kvm/id_regs.c | 284 ++++++++++++++++++++--------
> > 3 files changed, 203 insertions(+), 84 deletions(-)
> >
> > diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
> > index 6bf013fb110d..dc769c2eb7a4 100644
> > --- a/arch/arm64/include/asm/cpufeature.h
> > +++ b/arch/arm64/include/asm/cpufeature.h
> > @@ -915,6 +915,7 @@ static inline unsigned int get_vmid_bits(u64 mmfr1)
> > return 8;
> > }
> >
> > +s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, s64 cur);
> > struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id);
> >
> > extern struct arm64_ftr_override id_aa64mmfr1_override;
> > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> > index 2e3e55139777..677ec4fe9f6b 100644
> > --- a/arch/arm64/kernel/cpufeature.c
> > +++ b/arch/arm64/kernel/cpufeature.c
> > @@ -791,7 +791,7 @@ static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
> > return reg;
> > }
> >
> > -static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
> > +s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
> > s64 cur)
> > {
> > s64 ret = 0;
> > diff --git a/arch/arm64/kvm/id_regs.c b/arch/arm64/kvm/id_regs.c
> > index fe37b6786b4c..33968ada29bb 100644
> > --- a/arch/arm64/kvm/id_regs.c
> > +++ b/arch/arm64/kvm/id_regs.c
> > @@ -18,6 +18,66 @@
> >
> > #include "sys_regs.h"
> >
> > +/**
> > + * arm64_check_features() - Check if a feature register value constitutes
> > + * a subset of features indicated by the idreg's KVM sanitised limit.
> > + *
> > + * This function will check if each feature field of @val is the "safe" value
> > + * against idreg's KVM sanitised limit return from reset() callback.
> > + * If a field value in @val is the same as the one in limit, it is always
> > + * considered the safe value regardless For register fields that are not in
> > + * writable, only the value in limit is considered the safe value.
> > + *
> > + * Return: 0 if all the fields are safe. Otherwise, return negative errno.
> > + */
> > +static int arm64_check_features(struct kvm_vcpu *vcpu,
> > + const struct sys_reg_desc *rd,
> > + u64 val)
> > +{
> > + const struct arm64_ftr_reg *ftr_reg;
> > + const struct arm64_ftr_bits *ftrp = NULL;
> > + u32 id = reg_to_encoding(rd);
> > + u64 writable_mask = rd->val;
> > + u64 limit = 0;
> > + u64 mask = 0;
> > +
> > + /* For hidden and unallocated idregs without reset, only val = 0 is allowed. */
> > + if (rd->reset) {
> > + limit = rd->reset(vcpu, rd);
> > + ftr_reg = get_arm64_ftr_reg(id);
> > + if (!ftr_reg)
> > + return -EINVAL;
> > + ftrp = ftr_reg->ftr_bits;
> > + }
> > +
> > + for (; ftrp && ftrp->width; ftrp++) {
> > + s64 f_val, f_lim, safe_val;
> > + u64 ftr_mask;
> > +
> > + ftr_mask = arm64_ftr_mask(ftrp);
> > + if ((ftr_mask & writable_mask) != ftr_mask)
> > + continue;
> > +
> > + f_val = arm64_ftr_value(ftrp, val);
> > + f_lim = arm64_ftr_value(ftrp, limit);
> > + mask |= ftr_mask;
> > +
> > + if (f_val == f_lim)
> > + safe_val = f_val;
> > + else
> > + safe_val = arm64_ftr_safe_value(ftrp, f_val, f_lim);
>
> Since PMUVer and PerfMon is defined as FTR_EXACT, I believe having lower
> value in those two fields than the limit always ends up getting -E2BIG.
> Or am I missing something ??
> FYI. IIRC, we have some more fields in other ID registers that KVM
> shouldn't use as is.
Yes, you are right. I will add code to handle these exceptions.
>
> > +
> > + if (safe_val != f_val)
> > + return -E2BIG;
> > + }
> > +
> > + /* For fields that are not writable, values in limit are the safe values. */
> > + if ((val & ~mask) != (limit & ~mask))
> > + return -E2BIG;
> > +
> > + return 0;
> > +}
> > +
> > static u8 vcpu_pmuver(const struct kvm_vcpu *vcpu)
> > {
> > if (kvm_vcpu_has_pmu(vcpu))
> > @@ -68,7 +128,6 @@ u64 kvm_arm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id)
> > case SYS_ID_AA64PFR0_EL1:
> > if (!vcpu_has_sve(vcpu))
> > val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE);
> > - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU);
> > if (kvm_vgic_global_state.type == VGIC_V3) {
> > val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC);
> > val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC), 1);
> > @@ -95,15 +154,10 @@ u64 kvm_arm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id)
> > val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT);
> > break;
> > case SYS_ID_AA64DFR0_EL1:
> > - /* Limit debug to ARMv8.0 */
> > - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer);
> > - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), 6);
> > /* Set PMUver to the required version */
> > val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
> > val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer),
> > vcpu_pmuver(vcpu));
> > - /* Hide SPE from guests */
> > - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer);
> > break;
> > case SYS_ID_DFR0_EL1:
> > val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon);
> > @@ -162,9 +216,14 @@ static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
> > static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
> > u64 val)
> > {
> > - /* This is what we mean by invariant: you can't change it. */
> > - if (val != read_id_reg(vcpu, rd))
> > - return -EINVAL;
> > + u32 id = reg_to_encoding(rd);
> > + int ret;
> > +
> > + ret = arm64_check_features(vcpu, rd, val);
> > + if (ret)
> > + return ret;
> > +
> > + IDREG(vcpu->kvm, id) = val;
> >
> > return 0;
> > }
> > @@ -198,12 +257,40 @@ static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu,
> > return id_visibility(vcpu, r);
> > }
> >
> > +static u64 read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
> > + const struct sys_reg_desc *rd)
> > +{
> > + u64 val;
> > + u32 id = reg_to_encoding(rd);
> > +
> > + val = read_sanitised_ftr_reg(id);
> > + /*
> > + * The default is to expose CSV2 == 1 if the HW isn't affected.
> > + * Although this is a per-CPU feature, we make it global because
> > + * asymmetric systems are just a nuisance.
> > + *
> > + * Userspace can override this as long as it doesn't promise
> > + * the impossible.
> > + */
> > + if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) {
> > + val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2);
> > + val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2), 1);
> > + }
> > + if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) {
> > + val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3);
> > + val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3), 1);
> > + }
> > +
> > + val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU);
> > +
> > + return val;
> > +}
> > +
> > static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
> > const struct sys_reg_desc *rd,
> > u64 val)
> > {
> > u8 csv2, csv3;
> > - u64 sval = val;
> >
> > /*
> > * Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as
> > @@ -219,16 +306,30 @@ static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
> > if (csv3 > 1 || (csv3 && arm64_get_meltdown_state() != SPECTRE_UNAFFECTED))
> > return -EINVAL;
> >
> > - /* We can only differ with CSV[23], and anything else is an error */
> > - val ^= read_id_reg(vcpu, rd);
> > - val &= ~(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2) |
> > - ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3));
> > - if (val)
> > - return -EINVAL;
> > + return set_id_reg(vcpu, rd, val);
> > +}
> > +
> > +static u64 read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
> > + const struct sys_reg_desc *rd)
> > +{
> > + u64 val;
> > + u32 id = reg_to_encoding(rd);
> >
> > - IDREG(vcpu->kvm, reg_to_encoding(rd)) = sval;
> > + val = read_sanitised_ftr_reg(id);
> > + /* Limit debug to ARMv8.0 */
> > + val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer);
> > + val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), 6);
> > + /*
> > + * Initialise the default PMUver before there is a chance to
> > + * create an actual PMU.
> > + */
> > + val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
> > + val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer),
> > + kvm_arm_pmu_get_pmuver_limit());
> > + /* Hide SPE from guests */
> > + val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer);
> >
> > - return 0;
> > + return val;
> > }
> >
> > static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
> > @@ -237,6 +338,7 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
> > {
> > u8 pmuver, host_pmuver;
> > bool valid_pmu;
> > + int ret;
> >
> > host_pmuver = kvm_arm_pmu_get_pmuver_limit();
> >
> > @@ -256,36 +358,61 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
> > if (kvm_vcpu_has_pmu(vcpu) != valid_pmu)
> > return -EINVAL;
> >
> > - /* We can only differ with PMUver, and anything else is an error */
> > - val ^= read_id_reg(vcpu, rd);
> > - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
> > - if (val)
> > - return -EINVAL;
> > + if (!valid_pmu) {
> > + /*
> > + * Ignore the PMUVer filed in @val. The PMUVer would be determined
> > + * by arch flags bit KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU,
> > + */
> > + pmuver = FIELD_GET(ID_AA64DFR0_EL1_PMUVer_MASK, read_id_reg(vcpu, rd));
>
> As vPMU is not configured for this vCPU, I believe pmuver will be
> 0x0 or 0xf. I think that is not what we want there.
> Or am I missing something ?
As stated in the comment, when vPMU is not configured, the PMUVer
observed by the guest would be determined by arch flags bit
KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU. The value in the fields of idreg
doesn't matter. Here is just a trick to ignore the check for the
PMUVer field.
>
>
> > + val &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
> > + val |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK, pmuver);
> > + }
> >
> > - if (valid_pmu) {
> > - mutex_lock(&vcpu->kvm->arch.config_lock);
> > - IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
> > - IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK,
> > - pmuver);
> > + mutex_lock(&vcpu->kvm->arch.config_lock);
> >
> > - IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &= ~ID_DFR0_EL1_PerfMon_MASK;
> > - IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK,
> > - pmuver_to_perfmon(pmuver));
> > + ret = set_id_reg(vcpu, rd, val);
> > + if (ret) {
> > mutex_unlock(&vcpu->kvm->arch.config_lock);
> > - } else {
> > + return ret;
> > + }
> > +
> > + IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &= ~ID_DFR0_EL1_PerfMon_MASK;
> > + IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK,
> > + pmuver_to_perfmon(pmuver));
> > +
> > + if (!valid_pmu)
> > assign_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags,
> > pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF);
> > - }
> > +
> > + mutex_unlock(&vcpu->kvm->arch.config_lock);
> >
> > return 0;
> > }
> >
> > +static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu,
> > + const struct sys_reg_desc *rd)
> > +{
> > + u64 val;
> > + u32 id = reg_to_encoding(rd);
> > +
> > + val = read_sanitised_ftr_reg(id);
> > + /*
> > + * Initialise the default PMUver before there is a chance to
> > + * create an actual PMU.
> > + */
> > + val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon);
> > + val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), kvm_arm_pmu_get_pmuver_limit());
> > +
> > + return val;
> > +}
> > +
> > static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
> > const struct sys_reg_desc *rd,
> > u64 val)
> > {
> > u8 perfmon, host_perfmon;
> > bool valid_pmu;
> > + int ret;
> >
> > host_perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit());
> >
> > @@ -306,25 +433,33 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
> > if (kvm_vcpu_has_pmu(vcpu) != valid_pmu)
> > return -EINVAL;
> >
> > - /* We can only differ with PerfMon, and anything else is an error */
> > - val ^= read_id_reg(vcpu, rd);
> > - val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon);
> > - if (val)
> > - return -EINVAL;
> > + if (!valid_pmu) {
> > + /*
> > + * Ignore the PerfMon filed in @val. The PerfMon would be determined
> > + * by arch flags bit KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU,
> > + */
>
> I have the same comment as set_id_aa64dfr0_el1().
>
> Thank you,
> Reiji
>
> > + perfmon = FIELD_GET(ID_DFR0_EL1_PerfMon_MASK, read_id_reg(vcpu, rd));
> > + val &= ~ID_DFR0_EL1_PerfMon_MASK;
> > + val |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK, perfmon);
> > + }
> >
> > - if (valid_pmu) {
> > - mutex_lock(&vcpu->kvm->arch.config_lock);
> > - IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &= ~ID_DFR0_EL1_PerfMon_MASK;
> > - IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK, perfmon);
> > + mutex_lock(&vcpu->kvm->arch.config_lock);
> >
> > - IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
> > - IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK,
> > - perfmon_to_pmuver(perfmon));
> > + ret = set_id_reg(vcpu, rd, val);
> > + if (ret) {
> > mutex_unlock(&vcpu->kvm->arch.config_lock);
> > - } else {
> > + return ret;
> > + }
> > +
> > + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
> > + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK,
> > + perfmon_to_pmuver(perfmon));
> > +
> > + if (!valid_pmu)
> > assign_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags,
> > perfmon == ID_DFR0_EL1_PerfMon_IMPDEF);
> > - }
> > +
> > + mutex_unlock(&vcpu->kvm->arch.config_lock);
> >
> > return 0;
> > }
> > @@ -402,9 +537,13 @@ const struct sys_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = {
> > /* CRm=1 */
> > AA32_ID_SANITISED(ID_PFR0_EL1),
> > AA32_ID_SANITISED(ID_PFR1_EL1),
> > - { SYS_DESC(SYS_ID_DFR0_EL1), .access = access_id_reg,
> > - .get_user = get_id_reg, .set_user = set_id_dfr0_el1,
> > - .visibility = aa32_id_visibility, },
> > + { SYS_DESC(SYS_ID_DFR0_EL1),
> > + .access = access_id_reg,
> > + .get_user = get_id_reg,
> > + .set_user = set_id_dfr0_el1,
> > + .visibility = aa32_id_visibility,
> > + .reset = read_sanitised_id_dfr0_el1,
> > + .val = ID_DFR0_EL1_PerfMon_MASK, },
> > ID_HIDDEN(ID_AFR0_EL1),
> > AA32_ID_SANITISED(ID_MMFR0_EL1),
> > AA32_ID_SANITISED(ID_MMFR1_EL1),
> > @@ -433,8 +572,12 @@ const struct sys_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = {
> >
> > /* AArch64 ID registers */
> > /* CRm=4 */
> > - { SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg,
> > - .get_user = get_id_reg, .set_user = set_id_aa64pfr0_el1, },
> > + { SYS_DESC(SYS_ID_AA64PFR0_EL1),
> > + .access = access_id_reg,
> > + .get_user = get_id_reg,
> > + .set_user = set_id_aa64pfr0_el1,
> > + .reset = read_sanitised_id_aa64pfr0_el1,
> > + .val = ID_AA64PFR0_EL1_CSV2_MASK | ID_AA64PFR0_EL1_CSV3_MASK, },
> > ID_SANITISED(ID_AA64PFR1_EL1),
> > ID_UNALLOCATED(4, 2),
> > ID_UNALLOCATED(4, 3),
> > @@ -444,8 +587,12 @@ const struct sys_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = {
> > ID_UNALLOCATED(4, 7),
> >
> > /* CRm=5 */
> > - { SYS_DESC(SYS_ID_AA64DFR0_EL1), .access = access_id_reg,
> > - .get_user = get_id_reg, .set_user = set_id_aa64dfr0_el1, },
> > + { SYS_DESC(SYS_ID_AA64DFR0_EL1),
> > + .access = access_id_reg,
> > + .get_user = get_id_reg,
> > + .set_user = set_id_aa64dfr0_el1,
> > + .reset = read_sanitised_id_aa64dfr0_el1,
> > + .val = ID_AA64DFR0_EL1_PMUVer_MASK, },
> > ID_SANITISED(ID_AA64DFR1_EL1),
> > ID_UNALLOCATED(5, 2),
> > ID_UNALLOCATED(5, 3),
> > @@ -520,33 +667,4 @@ void kvm_arm_init_id_regs(struct kvm *kvm)
> >
> > IDREG(kvm, id) = val;
> > }
> > -
> > - /*
> > - * The default is to expose CSV2 == 1 if the HW isn't affected.
> > - * Although this is a per-CPU feature, we make it global because
> > - * asymmetric systems are just a nuisance.
> > - *
> > - * Userspace can override this as long as it doesn't promise
> > - * the impossible.
> > - */
> > - val = IDREG(kvm, SYS_ID_AA64PFR0_EL1);
> > -
> > - if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) {
> > - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2);
> > - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2), 1);
> > - }
> > - if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) {
> > - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3);
> > - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3), 1);
> > - }
> > -
> > - IDREG(kvm, SYS_ID_AA64PFR0_EL1) = val;
> > -
> > - /*
> > - * Initialise the default PMUver before there is a chance to
> > - * create an actual PMU.
> > - */
> > - IDREG(kvm, SYS_ID_AA64DFR0_EL1) &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
> > - IDREG(kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer),
> > - kvm_arm_pmu_get_pmuver_limit());
> > }
> > --
> > 2.40.0.348.gf938b09366-goog
> >
Thanks,
Jing
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^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v6 6/6] KVM: arm64: Refactor writings for PMUVer/CSV2/CSV3
2023-04-24 19:19 ` Jing Zhang
@ 2023-04-25 2:19 ` Reiji Watanabe
2023-04-25 16:40 ` Jing Zhang
0 siblings, 1 reply; 18+ messages in thread
From: Reiji Watanabe @ 2023-04-25 2:19 UTC (permalink / raw)
To: Jing Zhang
Cc: KVM, KVMARM, ARMLinux, Marc Zyngier, Oliver Upton, Will Deacon,
Paolo Bonzini, James Morse, Alexandru Elisei, Suzuki K Poulose,
Fuad Tabba, Raghavendra Rao Ananta
Hi Jing,
On Mon, Apr 24, 2023 at 12:19:50PM -0700, Jing Zhang wrote:
> Hi Reiji,
>
> On Tue, Apr 18, 2023 at 9:59 PM Reiji Watanabe <reijiw@google.com> wrote:
> >
> > Hi Jing,
> >
> > On Tue, Apr 04, 2023 at 03:53:44AM +0000, Jing Zhang wrote:
> > > Refactor writings for ID_AA64PFR0_EL1.[CSV2|CSV3],
> > > ID_AA64DFR0_EL1.PMUVer and ID_DFR0_ELF.PerfMon based on utilities
> > > introduced by ID register descriptor array.
> > >
> > > Signed-off-by: Jing Zhang <jingzhangos@google.com>
> > > ---
> > > arch/arm64/include/asm/cpufeature.h | 1 +
> > > arch/arm64/kernel/cpufeature.c | 2 +-
> > > arch/arm64/kvm/id_regs.c | 284 ++++++++++++++++++++--------
> > > 3 files changed, 203 insertions(+), 84 deletions(-)
> > >
> > > diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
> > > index 6bf013fb110d..dc769c2eb7a4 100644
> > > --- a/arch/arm64/include/asm/cpufeature.h
> > > +++ b/arch/arm64/include/asm/cpufeature.h
> > > @@ -915,6 +915,7 @@ static inline unsigned int get_vmid_bits(u64 mmfr1)
> > > return 8;
> > > }
> > >
> > > +s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, s64 cur);
> > > struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id);
> > >
> > > extern struct arm64_ftr_override id_aa64mmfr1_override;
> > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> > > index 2e3e55139777..677ec4fe9f6b 100644
> > > --- a/arch/arm64/kernel/cpufeature.c
> > > +++ b/arch/arm64/kernel/cpufeature.c
> > > @@ -791,7 +791,7 @@ static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
> > > return reg;
> > > }
> > >
> > > -static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
> > > +s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
> > > s64 cur)
> > > {
> > > s64 ret = 0;
> > > diff --git a/arch/arm64/kvm/id_regs.c b/arch/arm64/kvm/id_regs.c
> > > index fe37b6786b4c..33968ada29bb 100644
> > > --- a/arch/arm64/kvm/id_regs.c
> > > +++ b/arch/arm64/kvm/id_regs.c
> > > @@ -18,6 +18,66 @@
> > >
> > > #include "sys_regs.h"
> > >
> > > +/**
> > > + * arm64_check_features() - Check if a feature register value constitutes
> > > + * a subset of features indicated by the idreg's KVM sanitised limit.
> > > + *
> > > + * This function will check if each feature field of @val is the "safe" value
> > > + * against idreg's KVM sanitised limit return from reset() callback.
> > > + * If a field value in @val is the same as the one in limit, it is always
> > > + * considered the safe value regardless For register fields that are not in
> > > + * writable, only the value in limit is considered the safe value.
> > > + *
> > > + * Return: 0 if all the fields are safe. Otherwise, return negative errno.
> > > + */
> > > +static int arm64_check_features(struct kvm_vcpu *vcpu,
> > > + const struct sys_reg_desc *rd,
> > > + u64 val)
> > > +{
> > > + const struct arm64_ftr_reg *ftr_reg;
> > > + const struct arm64_ftr_bits *ftrp = NULL;
> > > + u32 id = reg_to_encoding(rd);
> > > + u64 writable_mask = rd->val;
> > > + u64 limit = 0;
> > > + u64 mask = 0;
> > > +
> > > + /* For hidden and unallocated idregs without reset, only val = 0 is allowed. */
> > > + if (rd->reset) {
> > > + limit = rd->reset(vcpu, rd);
> > > + ftr_reg = get_arm64_ftr_reg(id);
> > > + if (!ftr_reg)
> > > + return -EINVAL;
> > > + ftrp = ftr_reg->ftr_bits;
> > > + }
> > > +
> > > + for (; ftrp && ftrp->width; ftrp++) {
> > > + s64 f_val, f_lim, safe_val;
> > > + u64 ftr_mask;
> > > +
> > > + ftr_mask = arm64_ftr_mask(ftrp);
> > > + if ((ftr_mask & writable_mask) != ftr_mask)
> > > + continue;
> > > +
> > > + f_val = arm64_ftr_value(ftrp, val);
> > > + f_lim = arm64_ftr_value(ftrp, limit);
> > > + mask |= ftr_mask;
> > > +
> > > + if (f_val == f_lim)
> > > + safe_val = f_val;
> > > + else
> > > + safe_val = arm64_ftr_safe_value(ftrp, f_val, f_lim);
> >
> > Since PMUVer and PerfMon is defined as FTR_EXACT, I believe having lower
> > value in those two fields than the limit always ends up getting -E2BIG.
> > Or am I missing something ??
> > FYI. IIRC, we have some more fields in other ID registers that KVM
> > shouldn't use as is.
> Yes, you are right. I will add code to handle these exceptions.
> >
> > > +
> > > + if (safe_val != f_val)
> > > + return -E2BIG;
> > > + }
> > > +
> > > + /* For fields that are not writable, values in limit are the safe values. */
> > > + if ((val & ~mask) != (limit & ~mask))
> > > + return -E2BIG;
> > > +
> > > + return 0;
> > > +}
> > > +
> > > static u8 vcpu_pmuver(const struct kvm_vcpu *vcpu)
> > > {
> > > if (kvm_vcpu_has_pmu(vcpu))
> > > @@ -68,7 +128,6 @@ u64 kvm_arm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id)
> > > case SYS_ID_AA64PFR0_EL1:
> > > if (!vcpu_has_sve(vcpu))
> > > val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE);
> > > - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU);
> > > if (kvm_vgic_global_state.type == VGIC_V3) {
> > > val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC);
> > > val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC), 1);
> > > @@ -95,15 +154,10 @@ u64 kvm_arm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id)
> > > val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT);
> > > break;
> > > case SYS_ID_AA64DFR0_EL1:
> > > - /* Limit debug to ARMv8.0 */
> > > - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer);
> > > - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), 6);
> > > /* Set PMUver to the required version */
> > > val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
> > > val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer),
> > > vcpu_pmuver(vcpu));
> > > - /* Hide SPE from guests */
> > > - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer);
> > > break;
> > > case SYS_ID_DFR0_EL1:
> > > val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon);
> > > @@ -162,9 +216,14 @@ static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
> > > static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
> > > u64 val)
> > > {
> > > - /* This is what we mean by invariant: you can't change it. */
> > > - if (val != read_id_reg(vcpu, rd))
> > > - return -EINVAL;
> > > + u32 id = reg_to_encoding(rd);
> > > + int ret;
> > > +
> > > + ret = arm64_check_features(vcpu, rd, val);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + IDREG(vcpu->kvm, id) = val;
> > >
> > > return 0;
> > > }
> > > @@ -198,12 +257,40 @@ static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu,
> > > return id_visibility(vcpu, r);
> > > }
> > >
> > > +static u64 read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
> > > + const struct sys_reg_desc *rd)
> > > +{
> > > + u64 val;
> > > + u32 id = reg_to_encoding(rd);
> > > +
> > > + val = read_sanitised_ftr_reg(id);
> > > + /*
> > > + * The default is to expose CSV2 == 1 if the HW isn't affected.
> > > + * Although this is a per-CPU feature, we make it global because
> > > + * asymmetric systems are just a nuisance.
> > > + *
> > > + * Userspace can override this as long as it doesn't promise
> > > + * the impossible.
> > > + */
> > > + if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) {
> > > + val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2);
> > > + val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2), 1);
> > > + }
> > > + if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) {
> > > + val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3);
> > > + val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3), 1);
> > > + }
> > > +
> > > + val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU);
> > > +
> > > + return val;
> > > +}
> > > +
> > > static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
> > > const struct sys_reg_desc *rd,
> > > u64 val)
> > > {
> > > u8 csv2, csv3;
> > > - u64 sval = val;
> > >
> > > /*
> > > * Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as
> > > @@ -219,16 +306,30 @@ static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
> > > if (csv3 > 1 || (csv3 && arm64_get_meltdown_state() != SPECTRE_UNAFFECTED))
> > > return -EINVAL;
> > >
> > > - /* We can only differ with CSV[23], and anything else is an error */
> > > - val ^= read_id_reg(vcpu, rd);
> > > - val &= ~(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2) |
> > > - ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3));
> > > - if (val)
> > > - return -EINVAL;
> > > + return set_id_reg(vcpu, rd, val);
> > > +}
> > > +
> > > +static u64 read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
> > > + const struct sys_reg_desc *rd)
> > > +{
> > > + u64 val;
> > > + u32 id = reg_to_encoding(rd);
> > >
> > > - IDREG(vcpu->kvm, reg_to_encoding(rd)) = sval;
> > > + val = read_sanitised_ftr_reg(id);
> > > + /* Limit debug to ARMv8.0 */
> > > + val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer);
> > > + val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), 6);
> > > + /*
> > > + * Initialise the default PMUver before there is a chance to
> > > + * create an actual PMU.
> > > + */
> > > + val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
> > > + val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer),
> > > + kvm_arm_pmu_get_pmuver_limit());
> > > + /* Hide SPE from guests */
> > > + val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer);
> > >
> > > - return 0;
> > > + return val;
> > > }
> > >
> > > static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
> > > @@ -237,6 +338,7 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
> > > {
> > > u8 pmuver, host_pmuver;
> > > bool valid_pmu;
> > > + int ret;
> > >
> > > host_pmuver = kvm_arm_pmu_get_pmuver_limit();
> > >
> > > @@ -256,36 +358,61 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
> > > if (kvm_vcpu_has_pmu(vcpu) != valid_pmu)
> > > return -EINVAL;
> > >
> > > - /* We can only differ with PMUver, and anything else is an error */
> > > - val ^= read_id_reg(vcpu, rd);
> > > - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
> > > - if (val)
> > > - return -EINVAL;
> > > + if (!valid_pmu) {
> > > + /*
> > > + * Ignore the PMUVer filed in @val. The PMUVer would be determined
> > > + * by arch flags bit KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU,
> > > + */
> > > + pmuver = FIELD_GET(ID_AA64DFR0_EL1_PMUVer_MASK, read_id_reg(vcpu, rd));
> >
> > As vPMU is not configured for this vCPU, I believe pmuver will be
> > 0x0 or 0xf. I think that is not what we want there.
> > Or am I missing something ?
> As stated in the comment, when vPMU is not configured, the PMUVer
> observed by the guest would be determined by arch flags bit
> KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU. The value in the fields of idreg
> doesn't matter. Here is just a trick to ignore the check for the
> PMUVer field.
That sounds like what I understand. But, I still think the code is
different from that.
When we get here, this vcpu has no PMU. Since PMUVer in the @val is
already validated earlier in this function, PMUVer in the @val is
0 or 0xf. As this vcpu has no PMU, the "pmuver" (the current PMUVer
for this vcpu) is also 0 or 0xf. So, I wonder why the field in
@val needs to be updated with the "pmuver". Do you want to simply
clear the field or do you mean IDREG() instead of read_id_reg() ?
Thank you,
Reiji
> >
> >
> > > + val &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
> > > + val |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK, pmuver);
> > > + }
> > >
> > > - if (valid_pmu) {
> > > - mutex_lock(&vcpu->kvm->arch.config_lock);
> > > - IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
> > > - IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK,
> > > - pmuver);
> > > + mutex_lock(&vcpu->kvm->arch.config_lock);
> > >
> > > - IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &= ~ID_DFR0_EL1_PerfMon_MASK;
> > > - IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK,
> > > - pmuver_to_perfmon(pmuver));
> > > + ret = set_id_reg(vcpu, rd, val);
> > > + if (ret) {
> > > mutex_unlock(&vcpu->kvm->arch.config_lock);
> > > - } else {
> > > + return ret;
> > > + }
> > > +
> > > + IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &= ~ID_DFR0_EL1_PerfMon_MASK;
> > > + IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK,
> > > + pmuver_to_perfmon(pmuver));
> > > +
> > > + if (!valid_pmu)
> > > assign_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags,
> > > pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF);
> > > - }
> > > +
> > > + mutex_unlock(&vcpu->kvm->arch.config_lock);
> > >
> > > return 0;
> > > }
> > >
> > > +static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu,
> > > + const struct sys_reg_desc *rd)
> > > +{
> > > + u64 val;
> > > + u32 id = reg_to_encoding(rd);
> > > +
> > > + val = read_sanitised_ftr_reg(id);
> > > + /*
> > > + * Initialise the default PMUver before there is a chance to
> > > + * create an actual PMU.
> > > + */
> > > + val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon);
> > > + val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), kvm_arm_pmu_get_pmuver_limit());
> > > +
> > > + return val;
> > > +}
> > > +
> > > static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
> > > const struct sys_reg_desc *rd,
> > > u64 val)
> > > {
> > > u8 perfmon, host_perfmon;
> > > bool valid_pmu;
> > > + int ret;
> > >
> > > host_perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit());
> > >
> > > @@ -306,25 +433,33 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
> > > if (kvm_vcpu_has_pmu(vcpu) != valid_pmu)
> > > return -EINVAL;
> > >
> > > - /* We can only differ with PerfMon, and anything else is an error */
> > > - val ^= read_id_reg(vcpu, rd);
> > > - val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon);
> > > - if (val)
> > > - return -EINVAL;
> > > + if (!valid_pmu) {
> > > + /*
> > > + * Ignore the PerfMon filed in @val. The PerfMon would be determined
> > > + * by arch flags bit KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU,
> > > + */
> >
> > I have the same comment as set_id_aa64dfr0_el1().
> >
> > Thank you,
> > Reiji
> >
> > > + perfmon = FIELD_GET(ID_DFR0_EL1_PerfMon_MASK, read_id_reg(vcpu, rd));
> > > + val &= ~ID_DFR0_EL1_PerfMon_MASK;
> > > + val |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK, perfmon);
> > > + }
> > >
> > > - if (valid_pmu) {
> > > - mutex_lock(&vcpu->kvm->arch.config_lock);
> > > - IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &= ~ID_DFR0_EL1_PerfMon_MASK;
> > > - IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK, perfmon);
> > > + mutex_lock(&vcpu->kvm->arch.config_lock);
> > >
> > > - IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
> > > - IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK,
> > > - perfmon_to_pmuver(perfmon));
> > > + ret = set_id_reg(vcpu, rd, val);
> > > + if (ret) {
> > > mutex_unlock(&vcpu->kvm->arch.config_lock);
> > > - } else {
> > > + return ret;
> > > + }
> > > +
> > > + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
> > > + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK,
> > > + perfmon_to_pmuver(perfmon));
> > > +
> > > + if (!valid_pmu)
> > > assign_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags,
> > > perfmon == ID_DFR0_EL1_PerfMon_IMPDEF);
> > > - }
> > > +
> > > + mutex_unlock(&vcpu->kvm->arch.config_lock);
> > >
> > > return 0;
> > > }
> > > @@ -402,9 +537,13 @@ const struct sys_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = {
> > > /* CRm=1 */
> > > AA32_ID_SANITISED(ID_PFR0_EL1),
> > > AA32_ID_SANITISED(ID_PFR1_EL1),
> > > - { SYS_DESC(SYS_ID_DFR0_EL1), .access = access_id_reg,
> > > - .get_user = get_id_reg, .set_user = set_id_dfr0_el1,
> > > - .visibility = aa32_id_visibility, },
> > > + { SYS_DESC(SYS_ID_DFR0_EL1),
> > > + .access = access_id_reg,
> > > + .get_user = get_id_reg,
> > > + .set_user = set_id_dfr0_el1,
> > > + .visibility = aa32_id_visibility,
> > > + .reset = read_sanitised_id_dfr0_el1,
> > > + .val = ID_DFR0_EL1_PerfMon_MASK, },
> > > ID_HIDDEN(ID_AFR0_EL1),
> > > AA32_ID_SANITISED(ID_MMFR0_EL1),
> > > AA32_ID_SANITISED(ID_MMFR1_EL1),
> > > @@ -433,8 +572,12 @@ const struct sys_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = {
> > >
> > > /* AArch64 ID registers */
> > > /* CRm=4 */
> > > - { SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg,
> > > - .get_user = get_id_reg, .set_user = set_id_aa64pfr0_el1, },
> > > + { SYS_DESC(SYS_ID_AA64PFR0_EL1),
> > > + .access = access_id_reg,
> > > + .get_user = get_id_reg,
> > > + .set_user = set_id_aa64pfr0_el1,
> > > + .reset = read_sanitised_id_aa64pfr0_el1,
> > > + .val = ID_AA64PFR0_EL1_CSV2_MASK | ID_AA64PFR0_EL1_CSV3_MASK, },
> > > ID_SANITISED(ID_AA64PFR1_EL1),
> > > ID_UNALLOCATED(4, 2),
> > > ID_UNALLOCATED(4, 3),
> > > @@ -444,8 +587,12 @@ const struct sys_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = {
> > > ID_UNALLOCATED(4, 7),
> > >
> > > /* CRm=5 */
> > > - { SYS_DESC(SYS_ID_AA64DFR0_EL1), .access = access_id_reg,
> > > - .get_user = get_id_reg, .set_user = set_id_aa64dfr0_el1, },
> > > + { SYS_DESC(SYS_ID_AA64DFR0_EL1),
> > > + .access = access_id_reg,
> > > + .get_user = get_id_reg,
> > > + .set_user = set_id_aa64dfr0_el1,
> > > + .reset = read_sanitised_id_aa64dfr0_el1,
> > > + .val = ID_AA64DFR0_EL1_PMUVer_MASK, },
> > > ID_SANITISED(ID_AA64DFR1_EL1),
> > > ID_UNALLOCATED(5, 2),
> > > ID_UNALLOCATED(5, 3),
> > > @@ -520,33 +667,4 @@ void kvm_arm_init_id_regs(struct kvm *kvm)
> > >
> > > IDREG(kvm, id) = val;
> > > }
> > > -
> > > - /*
> > > - * The default is to expose CSV2 == 1 if the HW isn't affected.
> > > - * Although this is a per-CPU feature, we make it global because
> > > - * asymmetric systems are just a nuisance.
> > > - *
> > > - * Userspace can override this as long as it doesn't promise
> > > - * the impossible.
> > > - */
> > > - val = IDREG(kvm, SYS_ID_AA64PFR0_EL1);
> > > -
> > > - if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) {
> > > - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2);
> > > - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2), 1);
> > > - }
> > > - if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) {
> > > - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3);
> > > - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3), 1);
> > > - }
> > > -
> > > - IDREG(kvm, SYS_ID_AA64PFR0_EL1) = val;
> > > -
> > > - /*
> > > - * Initialise the default PMUver before there is a chance to
> > > - * create an actual PMU.
> > > - */
> > > - IDREG(kvm, SYS_ID_AA64DFR0_EL1) &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
> > > - IDREG(kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer),
> > > - kvm_arm_pmu_get_pmuver_limit());
> > > }
> > > --
> > > 2.40.0.348.gf938b09366-goog
> > >
> Thanks,
> Jing
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v6 6/6] KVM: arm64: Refactor writings for PMUVer/CSV2/CSV3
2023-04-25 2:19 ` Reiji Watanabe
@ 2023-04-25 16:40 ` Jing Zhang
0 siblings, 0 replies; 18+ messages in thread
From: Jing Zhang @ 2023-04-25 16:40 UTC (permalink / raw)
To: Reiji Watanabe
Cc: KVM, KVMARM, ARMLinux, Marc Zyngier, Oliver Upton, Will Deacon,
Paolo Bonzini, James Morse, Alexandru Elisei, Suzuki K Poulose,
Fuad Tabba, Raghavendra Rao Ananta
Hi Reiji,
On Mon, Apr 24, 2023 at 7:19 PM Reiji Watanabe <reijiw@google.com> wrote:
>
> Hi Jing,
>
> On Mon, Apr 24, 2023 at 12:19:50PM -0700, Jing Zhang wrote:
> > Hi Reiji,
> >
> > On Tue, Apr 18, 2023 at 9:59 PM Reiji Watanabe <reijiw@google.com> wrote:
> > >
> > > Hi Jing,
> > >
> > > On Tue, Apr 04, 2023 at 03:53:44AM +0000, Jing Zhang wrote:
> > > > Refactor writings for ID_AA64PFR0_EL1.[CSV2|CSV3],
> > > > ID_AA64DFR0_EL1.PMUVer and ID_DFR0_ELF.PerfMon based on utilities
> > > > introduced by ID register descriptor array.
> > > >
> > > > Signed-off-by: Jing Zhang <jingzhangos@google.com>
> > > > ---
> > > > arch/arm64/include/asm/cpufeature.h | 1 +
> > > > arch/arm64/kernel/cpufeature.c | 2 +-
> > > > arch/arm64/kvm/id_regs.c | 284 ++++++++++++++++++++--------
> > > > 3 files changed, 203 insertions(+), 84 deletions(-)
> > > >
> > > > diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
> > > > index 6bf013fb110d..dc769c2eb7a4 100644
> > > > --- a/arch/arm64/include/asm/cpufeature.h
> > > > +++ b/arch/arm64/include/asm/cpufeature.h
> > > > @@ -915,6 +915,7 @@ static inline unsigned int get_vmid_bits(u64 mmfr1)
> > > > return 8;
> > > > }
> > > >
> > > > +s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, s64 cur);
> > > > struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id);
> > > >
> > > > extern struct arm64_ftr_override id_aa64mmfr1_override;
> > > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> > > > index 2e3e55139777..677ec4fe9f6b 100644
> > > > --- a/arch/arm64/kernel/cpufeature.c
> > > > +++ b/arch/arm64/kernel/cpufeature.c
> > > > @@ -791,7 +791,7 @@ static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
> > > > return reg;
> > > > }
> > > >
> > > > -static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
> > > > +s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
> > > > s64 cur)
> > > > {
> > > > s64 ret = 0;
> > > > diff --git a/arch/arm64/kvm/id_regs.c b/arch/arm64/kvm/id_regs.c
> > > > index fe37b6786b4c..33968ada29bb 100644
> > > > --- a/arch/arm64/kvm/id_regs.c
> > > > +++ b/arch/arm64/kvm/id_regs.c
> > > > @@ -18,6 +18,66 @@
> > > >
> > > > #include "sys_regs.h"
> > > >
> > > > +/**
> > > > + * arm64_check_features() - Check if a feature register value constitutes
> > > > + * a subset of features indicated by the idreg's KVM sanitised limit.
> > > > + *
> > > > + * This function will check if each feature field of @val is the "safe" value
> > > > + * against idreg's KVM sanitised limit return from reset() callback.
> > > > + * If a field value in @val is the same as the one in limit, it is always
> > > > + * considered the safe value regardless For register fields that are not in
> > > > + * writable, only the value in limit is considered the safe value.
> > > > + *
> > > > + * Return: 0 if all the fields are safe. Otherwise, return negative errno.
> > > > + */
> > > > +static int arm64_check_features(struct kvm_vcpu *vcpu,
> > > > + const struct sys_reg_desc *rd,
> > > > + u64 val)
> > > > +{
> > > > + const struct arm64_ftr_reg *ftr_reg;
> > > > + const struct arm64_ftr_bits *ftrp = NULL;
> > > > + u32 id = reg_to_encoding(rd);
> > > > + u64 writable_mask = rd->val;
> > > > + u64 limit = 0;
> > > > + u64 mask = 0;
> > > > +
> > > > + /* For hidden and unallocated idregs without reset, only val = 0 is allowed. */
> > > > + if (rd->reset) {
> > > > + limit = rd->reset(vcpu, rd);
> > > > + ftr_reg = get_arm64_ftr_reg(id);
> > > > + if (!ftr_reg)
> > > > + return -EINVAL;
> > > > + ftrp = ftr_reg->ftr_bits;
> > > > + }
> > > > +
> > > > + for (; ftrp && ftrp->width; ftrp++) {
> > > > + s64 f_val, f_lim, safe_val;
> > > > + u64 ftr_mask;
> > > > +
> > > > + ftr_mask = arm64_ftr_mask(ftrp);
> > > > + if ((ftr_mask & writable_mask) != ftr_mask)
> > > > + continue;
> > > > +
> > > > + f_val = arm64_ftr_value(ftrp, val);
> > > > + f_lim = arm64_ftr_value(ftrp, limit);
> > > > + mask |= ftr_mask;
> > > > +
> > > > + if (f_val == f_lim)
> > > > + safe_val = f_val;
> > > > + else
> > > > + safe_val = arm64_ftr_safe_value(ftrp, f_val, f_lim);
> > >
> > > Since PMUVer and PerfMon is defined as FTR_EXACT, I believe having lower
> > > value in those two fields than the limit always ends up getting -E2BIG.
> > > Or am I missing something ??
> > > FYI. IIRC, we have some more fields in other ID registers that KVM
> > > shouldn't use as is.
> > Yes, you are right. I will add code to handle these exceptions.
> > >
> > > > +
> > > > + if (safe_val != f_val)
> > > > + return -E2BIG;
> > > > + }
> > > > +
> > > > + /* For fields that are not writable, values in limit are the safe values. */
> > > > + if ((val & ~mask) != (limit & ~mask))
> > > > + return -E2BIG;
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > static u8 vcpu_pmuver(const struct kvm_vcpu *vcpu)
> > > > {
> > > > if (kvm_vcpu_has_pmu(vcpu))
> > > > @@ -68,7 +128,6 @@ u64 kvm_arm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id)
> > > > case SYS_ID_AA64PFR0_EL1:
> > > > if (!vcpu_has_sve(vcpu))
> > > > val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE);
> > > > - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU);
> > > > if (kvm_vgic_global_state.type == VGIC_V3) {
> > > > val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC);
> > > > val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC), 1);
> > > > @@ -95,15 +154,10 @@ u64 kvm_arm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id)
> > > > val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT);
> > > > break;
> > > > case SYS_ID_AA64DFR0_EL1:
> > > > - /* Limit debug to ARMv8.0 */
> > > > - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer);
> > > > - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), 6);
> > > > /* Set PMUver to the required version */
> > > > val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
> > > > val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer),
> > > > vcpu_pmuver(vcpu));
> > > > - /* Hide SPE from guests */
> > > > - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer);
> > > > break;
> > > > case SYS_ID_DFR0_EL1:
> > > > val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon);
> > > > @@ -162,9 +216,14 @@ static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
> > > > static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
> > > > u64 val)
> > > > {
> > > > - /* This is what we mean by invariant: you can't change it. */
> > > > - if (val != read_id_reg(vcpu, rd))
> > > > - return -EINVAL;
> > > > + u32 id = reg_to_encoding(rd);
> > > > + int ret;
> > > > +
> > > > + ret = arm64_check_features(vcpu, rd, val);
> > > > + if (ret)
> > > > + return ret;
> > > > +
> > > > + IDREG(vcpu->kvm, id) = val;
> > > >
> > > > return 0;
> > > > }
> > > > @@ -198,12 +257,40 @@ static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu,
> > > > return id_visibility(vcpu, r);
> > > > }
> > > >
> > > > +static u64 read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
> > > > + const struct sys_reg_desc *rd)
> > > > +{
> > > > + u64 val;
> > > > + u32 id = reg_to_encoding(rd);
> > > > +
> > > > + val = read_sanitised_ftr_reg(id);
> > > > + /*
> > > > + * The default is to expose CSV2 == 1 if the HW isn't affected.
> > > > + * Although this is a per-CPU feature, we make it global because
> > > > + * asymmetric systems are just a nuisance.
> > > > + *
> > > > + * Userspace can override this as long as it doesn't promise
> > > > + * the impossible.
> > > > + */
> > > > + if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) {
> > > > + val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2);
> > > > + val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2), 1);
> > > > + }
> > > > + if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) {
> > > > + val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3);
> > > > + val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3), 1);
> > > > + }
> > > > +
> > > > + val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU);
> > > > +
> > > > + return val;
> > > > +}
> > > > +
> > > > static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
> > > > const struct sys_reg_desc *rd,
> > > > u64 val)
> > > > {
> > > > u8 csv2, csv3;
> > > > - u64 sval = val;
> > > >
> > > > /*
> > > > * Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as
> > > > @@ -219,16 +306,30 @@ static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
> > > > if (csv3 > 1 || (csv3 && arm64_get_meltdown_state() != SPECTRE_UNAFFECTED))
> > > > return -EINVAL;
> > > >
> > > > - /* We can only differ with CSV[23], and anything else is an error */
> > > > - val ^= read_id_reg(vcpu, rd);
> > > > - val &= ~(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2) |
> > > > - ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3));
> > > > - if (val)
> > > > - return -EINVAL;
> > > > + return set_id_reg(vcpu, rd, val);
> > > > +}
> > > > +
> > > > +static u64 read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
> > > > + const struct sys_reg_desc *rd)
> > > > +{
> > > > + u64 val;
> > > > + u32 id = reg_to_encoding(rd);
> > > >
> > > > - IDREG(vcpu->kvm, reg_to_encoding(rd)) = sval;
> > > > + val = read_sanitised_ftr_reg(id);
> > > > + /* Limit debug to ARMv8.0 */
> > > > + val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer);
> > > > + val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), 6);
> > > > + /*
> > > > + * Initialise the default PMUver before there is a chance to
> > > > + * create an actual PMU.
> > > > + */
> > > > + val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
> > > > + val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer),
> > > > + kvm_arm_pmu_get_pmuver_limit());
> > > > + /* Hide SPE from guests */
> > > > + val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer);
> > > >
> > > > - return 0;
> > > > + return val;
> > > > }
> > > >
> > > > static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
> > > > @@ -237,6 +338,7 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
> > > > {
> > > > u8 pmuver, host_pmuver;
> > > > bool valid_pmu;
> > > > + int ret;
> > > >
> > > > host_pmuver = kvm_arm_pmu_get_pmuver_limit();
> > > >
> > > > @@ -256,36 +358,61 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
> > > > if (kvm_vcpu_has_pmu(vcpu) != valid_pmu)
> > > > return -EINVAL;
> > > >
> > > > - /* We can only differ with PMUver, and anything else is an error */
> > > > - val ^= read_id_reg(vcpu, rd);
> > > > - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
> > > > - if (val)
> > > > - return -EINVAL;
> > > > + if (!valid_pmu) {
> > > > + /*
> > > > + * Ignore the PMUVer filed in @val. The PMUVer would be determined
> > > > + * by arch flags bit KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU,
> > > > + */
> > > > + pmuver = FIELD_GET(ID_AA64DFR0_EL1_PMUVer_MASK, read_id_reg(vcpu, rd));
> > >
> > > As vPMU is not configured for this vCPU, I believe pmuver will be
> > > 0x0 or 0xf. I think that is not what we want there.
> > > Or am I missing something ?
> > As stated in the comment, when vPMU is not configured, the PMUVer
> > observed by the guest would be determined by arch flags bit
> > KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU. The value in the fields of idreg
> > doesn't matter. Here is just a trick to ignore the check for the
> > PMUVer field.
>
> That sounds like what I understand. But, I still think the code is
> different from that.
> When we get here, this vcpu has no PMU. Since PMUVer in the @val is
> already validated earlier in this function, PMUVer in the @val is
> 0 or 0xf. As this vcpu has no PMU, the "pmuver" (the current PMUVer
> for this vcpu) is also 0 or 0xf. So, I wonder why the field in
> @val needs to be updated with the "pmuver". Do you want to simply
> clear the field or do you mean IDREG() instead of read_id_reg() ?
Update the @val with the "pmuver" is to let the @val pass the
arm64_check_features called in set_id_reg. Otherwise, we need to keep
the code to check if PMUVer field is the only change. Marc has strong
objection to keep that code.
>
> Thank you,
> Reiji
>
> > >
> > >
> > > > + val &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
> > > > + val |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK, pmuver);
> > > > + }
> > > >
> > > > - if (valid_pmu) {
> > > > - mutex_lock(&vcpu->kvm->arch.config_lock);
> > > > - IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
> > > > - IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK,
> > > > - pmuver);
> > > > + mutex_lock(&vcpu->kvm->arch.config_lock);
> > > >
> > > > - IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &= ~ID_DFR0_EL1_PerfMon_MASK;
> > > > - IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK,
> > > > - pmuver_to_perfmon(pmuver));
> > > > + ret = set_id_reg(vcpu, rd, val);
> > > > + if (ret) {
> > > > mutex_unlock(&vcpu->kvm->arch.config_lock);
> > > > - } else {
> > > > + return ret;
> > > > + }
> > > > +
> > > > + IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &= ~ID_DFR0_EL1_PerfMon_MASK;
> > > > + IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK,
> > > > + pmuver_to_perfmon(pmuver));
> > > > +
> > > > + if (!valid_pmu)
> > > > assign_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags,
> > > > pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF);
> > > > - }
> > > > +
> > > > + mutex_unlock(&vcpu->kvm->arch.config_lock);
> > > >
> > > > return 0;
> > > > }
> > > >
> > > > +static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu,
> > > > + const struct sys_reg_desc *rd)
> > > > +{
> > > > + u64 val;
> > > > + u32 id = reg_to_encoding(rd);
> > > > +
> > > > + val = read_sanitised_ftr_reg(id);
> > > > + /*
> > > > + * Initialise the default PMUver before there is a chance to
> > > > + * create an actual PMU.
> > > > + */
> > > > + val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon);
> > > > + val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), kvm_arm_pmu_get_pmuver_limit());
> > > > +
> > > > + return val;
> > > > +}
> > > > +
> > > > static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
> > > > const struct sys_reg_desc *rd,
> > > > u64 val)
> > > > {
> > > > u8 perfmon, host_perfmon;
> > > > bool valid_pmu;
> > > > + int ret;
> > > >
> > > > host_perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit());
> > > >
> > > > @@ -306,25 +433,33 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
> > > > if (kvm_vcpu_has_pmu(vcpu) != valid_pmu)
> > > > return -EINVAL;
> > > >
> > > > - /* We can only differ with PerfMon, and anything else is an error */
> > > > - val ^= read_id_reg(vcpu, rd);
> > > > - val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon);
> > > > - if (val)
> > > > - return -EINVAL;
> > > > + if (!valid_pmu) {
> > > > + /*
> > > > + * Ignore the PerfMon filed in @val. The PerfMon would be determined
> > > > + * by arch flags bit KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU,
> > > > + */
> > >
> > > I have the same comment as set_id_aa64dfr0_el1().
> > >
> > > Thank you,
> > > Reiji
> > >
> > > > + perfmon = FIELD_GET(ID_DFR0_EL1_PerfMon_MASK, read_id_reg(vcpu, rd));
> > > > + val &= ~ID_DFR0_EL1_PerfMon_MASK;
> > > > + val |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK, perfmon);
> > > > + }
> > > >
> > > > - if (valid_pmu) {
> > > > - mutex_lock(&vcpu->kvm->arch.config_lock);
> > > > - IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &= ~ID_DFR0_EL1_PerfMon_MASK;
> > > > - IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |= FIELD_PREP(ID_DFR0_EL1_PerfMon_MASK, perfmon);
> > > > + mutex_lock(&vcpu->kvm->arch.config_lock);
> > > >
> > > > - IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
> > > > - IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK,
> > > > - perfmon_to_pmuver(perfmon));
> > > > + ret = set_id_reg(vcpu, rd, val);
> > > > + if (ret) {
> > > > mutex_unlock(&vcpu->kvm->arch.config_lock);
> > > > - } else {
> > > > + return ret;
> > > > + }
> > > > +
> > > > + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
> > > > + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK,
> > > > + perfmon_to_pmuver(perfmon));
> > > > +
> > > > + if (!valid_pmu)
> > > > assign_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags,
> > > > perfmon == ID_DFR0_EL1_PerfMon_IMPDEF);
> > > > - }
> > > > +
> > > > + mutex_unlock(&vcpu->kvm->arch.config_lock);
> > > >
> > > > return 0;
> > > > }
> > > > @@ -402,9 +537,13 @@ const struct sys_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = {
> > > > /* CRm=1 */
> > > > AA32_ID_SANITISED(ID_PFR0_EL1),
> > > > AA32_ID_SANITISED(ID_PFR1_EL1),
> > > > - { SYS_DESC(SYS_ID_DFR0_EL1), .access = access_id_reg,
> > > > - .get_user = get_id_reg, .set_user = set_id_dfr0_el1,
> > > > - .visibility = aa32_id_visibility, },
> > > > + { SYS_DESC(SYS_ID_DFR0_EL1),
> > > > + .access = access_id_reg,
> > > > + .get_user = get_id_reg,
> > > > + .set_user = set_id_dfr0_el1,
> > > > + .visibility = aa32_id_visibility,
> > > > + .reset = read_sanitised_id_dfr0_el1,
> > > > + .val = ID_DFR0_EL1_PerfMon_MASK, },
> > > > ID_HIDDEN(ID_AFR0_EL1),
> > > > AA32_ID_SANITISED(ID_MMFR0_EL1),
> > > > AA32_ID_SANITISED(ID_MMFR1_EL1),
> > > > @@ -433,8 +572,12 @@ const struct sys_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = {
> > > >
> > > > /* AArch64 ID registers */
> > > > /* CRm=4 */
> > > > - { SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg,
> > > > - .get_user = get_id_reg, .set_user = set_id_aa64pfr0_el1, },
> > > > + { SYS_DESC(SYS_ID_AA64PFR0_EL1),
> > > > + .access = access_id_reg,
> > > > + .get_user = get_id_reg,
> > > > + .set_user = set_id_aa64pfr0_el1,
> > > > + .reset = read_sanitised_id_aa64pfr0_el1,
> > > > + .val = ID_AA64PFR0_EL1_CSV2_MASK | ID_AA64PFR0_EL1_CSV3_MASK, },
> > > > ID_SANITISED(ID_AA64PFR1_EL1),
> > > > ID_UNALLOCATED(4, 2),
> > > > ID_UNALLOCATED(4, 3),
> > > > @@ -444,8 +587,12 @@ const struct sys_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = {
> > > > ID_UNALLOCATED(4, 7),
> > > >
> > > > /* CRm=5 */
> > > > - { SYS_DESC(SYS_ID_AA64DFR0_EL1), .access = access_id_reg,
> > > > - .get_user = get_id_reg, .set_user = set_id_aa64dfr0_el1, },
> > > > + { SYS_DESC(SYS_ID_AA64DFR0_EL1),
> > > > + .access = access_id_reg,
> > > > + .get_user = get_id_reg,
> > > > + .set_user = set_id_aa64dfr0_el1,
> > > > + .reset = read_sanitised_id_aa64dfr0_el1,
> > > > + .val = ID_AA64DFR0_EL1_PMUVer_MASK, },
> > > > ID_SANITISED(ID_AA64DFR1_EL1),
> > > > ID_UNALLOCATED(5, 2),
> > > > ID_UNALLOCATED(5, 3),
> > > > @@ -520,33 +667,4 @@ void kvm_arm_init_id_regs(struct kvm *kvm)
> > > >
> > > > IDREG(kvm, id) = val;
> > > > }
> > > > -
> > > > - /*
> > > > - * The default is to expose CSV2 == 1 if the HW isn't affected.
> > > > - * Although this is a per-CPU feature, we make it global because
> > > > - * asymmetric systems are just a nuisance.
> > > > - *
> > > > - * Userspace can override this as long as it doesn't promise
> > > > - * the impossible.
> > > > - */
> > > > - val = IDREG(kvm, SYS_ID_AA64PFR0_EL1);
> > > > -
> > > > - if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) {
> > > > - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2);
> > > > - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2), 1);
> > > > - }
> > > > - if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) {
> > > > - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3);
> > > > - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3), 1);
> > > > - }
> > > > -
> > > > - IDREG(kvm, SYS_ID_AA64PFR0_EL1) = val;
> > > > -
> > > > - /*
> > > > - * Initialise the default PMUver before there is a chance to
> > > > - * create an actual PMU.
> > > > - */
> > > > - IDREG(kvm, SYS_ID_AA64DFR0_EL1) &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
> > > > - IDREG(kvm, SYS_ID_AA64DFR0_EL1) |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer),
> > > > - kvm_arm_pmu_get_pmuver_limit());
> > > > }
> > > > --
> > > > 2.40.0.348.gf938b09366-goog
> > > >
> > Thanks,
> > Jing
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