From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A7806C77B73 for ; Wed, 19 Apr 2023 08:48:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=S6n5BLFdo6aMyDxYhP7GntQPYoGpuIUGJmhVSWC53ao=; b=r7Kt6X71vhPbWG TPjhM2VAe1Do6mCbk/n56skyXqz24OmGpzfkxKKBh4BzEdk/XGA85Ry4l1BD9WF+1gdtTyoKwYV4J IaA6gUieBoNfvCORRgze9mxE63ERo0d378zltj+0g7pqr07S7WKotQTnK/bq4xzy1L68vPG6fiZ2b dEjwoHUrQhR5R+YhZibOVR002rP47JXk6w6SDZ4+etpUo9Xtp/rmYFk5WOELmRZEU0/tFQNw0gY0d u5Pwv+vwKaRhax5AsQzk0oYiYAy6UfZnILU2uS+H1EplUoH5s9XtdlJOxPLTxwrR/4NEHwq4GOkQg C3zSPbMDfH1r1nNpzzPw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pp3U3-004ddv-2w; Wed, 19 Apr 2023 08:48:11 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pp3U0-004dZc-3B for linux-arm-kernel@lists.infradead.org; Wed, 19 Apr 2023 08:48:11 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F13A6143D; Wed, 19 Apr 2023 01:48:43 -0700 (PDT) Received: from bogus (unknown [10.57.57.81]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 031EB3F587; Wed, 19 Apr 2023 01:47:58 -0700 (PDT) Date: Wed, 19 Apr 2023 09:47:56 +0100 From: Sudeep Holla To: Ayan Kumar Halder Cc: mark.rutland@arm.com, lpieralisi@kernel.org, Sudeep Holla , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Vladimir Murzin , Stefano Stabellini Subject: Re: SMP enablement on Cortex-R52 (using PSCI ?) Message-ID: <20230419084756.3gypfyuuezjj7tyd@bogus> References: <1cb7d428-c047-1485-e39d-465806f6ef0b@amd.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1cb7d428-c047-1485-e39d-465806f6ef0b@amd.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230419_014809_095033_8E3194FE X-CRM114-Status: GOOD ( 22.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Ayan, On Fri, Apr 14, 2023 at 12:24:38PM +0100, Ayan Kumar Halder wrote: > Hi PSCI developers, > = > We have a SoC where there are 4 Cortex-R52 which is distributed in two > clusters. So we have 2 Cortex-R52 in one cluster and 2 Cortex-R52 in anot= her > cluster. > = > We wish to enable SMP on the 2 R52 within a cluster with Xen hypervisor (= EL2 > software) running on them. > = > We are trying to explore if we can use PSCI for booting the secondary cor= es. > = > Refer Cortex-R52 TRM > (https://developer.arm.com/documentation/100026/0101/?lang=3Den ), it > specifies the following :- > = > Page 24 - Section 1.4.1 > = > "Support for Exception levels, EL0, EL1, and EL2." > = > Page 30 - Section 2.1.6 > = > "The Cortex-R52 processor does not implement TrustZone=AE technology. It = does > not support the ability to distinguish between secure and non-secure > physical memories." > = > Thus, there is no EL3 and secure world in Cortex-R52. It implements > AArch32-V8R architecture. > KVM hypervisor use PSCI to bring up secondaries in the VMs. So I am sure we must be able to use the interface on Cortex-R52 without EL3. > = > Refer PSCI design document, > https://developer.arm.com/documentation/den0022/e/?lang=3Den > = > Page 18 - > "The PSCI specification focuses on the interface between Security states = for > power management. It provides a method for issuing power management > requests. To deal with the requests, the PPF must include a PSCI > implementation. A PSCI implementation might require communication between > the PPF and a Trusted OS or SP." > = > Page 17 - Privileged Platform Firmware (PPF) > = > "For Armv7 systems, or Armv8 systems using AArch32 at EL3, PPF executes in > EL3." > = > From the above two statements, I infer that PSCI requires a PPF (running = at > EL3) and a Trusted OS (running at secure EL2). If this is correct, then R= 52=A0 > cannot support PSCI. Please correct me if I am mistaken. > = > I wish to know how do we wake up the secondary core if PSCI is not > supported. > I will check with the authors if EL3 is a must for PSCI implementation, but IMO it must not be though every aspects described in the spec may not apply when used across EL2/EL1 boundaries especially when EL3 is not implemented in the hardware. -- = Regards, Sudeep _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel