From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, kvm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Cc: Alexandru Elisei <alexandru.elisei@arm.com>,
Andre Przywara <andre.przywara@arm.com>,
Chase Conklin <chase.conklin@arm.com>,
Christoffer Dall <christoffer.dall@arm.com>,
Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com>,
Darren Hart <darren@os.amperecomputing.com>,
Jintack Lim <jintack@cs.columbia.edu>,
Russell King <rmk+kernel@armlinux.org.uk>,
Miguel Luis <miguel.luis@oracle.com>,
James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
Zenghui Yu <yuzenghui@huawei.com>
Subject: [PATCH v10 12/59] KVM: arm64: nv: Add trap forwarding for MDCR_EL2
Date: Mon, 15 May 2023 18:30:16 +0100 [thread overview]
Message-ID: <20230515173103.1017669-13-maz@kernel.org> (raw)
In-Reply-To: <20230515173103.1017669-1-maz@kernel.org>
Describe the MDCR_EL2 register, and associate it with all the sysregs
it allows to trap.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/kvm/emulate-nested.c | 204 ++++++++++++++++++++++++++++++++
1 file changed, 204 insertions(+)
diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
index 8be331e5de9d..1e2fe192c9a4 100644
--- a/arch/arm64/kvm/emulate-nested.c
+++ b/arch/arm64/kvm/emulate-nested.c
@@ -65,6 +65,18 @@ enum coarse_grain_trap_id {
CGT_HCR_TTLBIS,
CGT_HCR_TTLBOS,
+ CGT_MDCR_TPMCR,
+ CGT_MDCR_TPM,
+ CGT_MDCR_TDE,
+ CGT_MDCR_TDA,
+ CGT_MDCR_TDOSA,
+ CGT_MDCR_TDRA,
+ CGT_MDCR_E2PB,
+ CGT_MDCR_TPMS,
+ CGT_MDCR_TTRF,
+ CGT_MDCR_E2TB,
+ CGT_MDCR_TDCC,
+
/*
* Anything after this point is a combination of trap controls,
* which all must be evaluated to decide what to do.
@@ -78,6 +90,11 @@ enum coarse_grain_trap_id {
CGT_HCR_TPU_TICAB,
CGT_HCR_TPU_TOCU,
CGT_HCR_NV1_ENSCXT,
+ CGT_MDCR_TPM_TPMCR,
+ CGT_MDCR_TDE_TDA,
+ CGT_MDCR_TDE_TDOSA,
+ CGT_MDCR_TDE_TDRA,
+ CGT_MDCR_TDCC_TDE_TDA,
/*
* Anything after this point requires a callback evaluating a
@@ -249,6 +266,72 @@ static const struct trap_bits coarse_trap_bits[] = {
.mask = HCR_TTLBOS,
.behaviour = BEHAVE_FORWARD_ANY,
},
+ [CGT_MDCR_TPMCR] = {
+ .index = MDCR_EL2,
+ .value = MDCR_EL2_TPMCR,
+ .mask = MDCR_EL2_TPMCR,
+ .behaviour = BEHAVE_FORWARD_ANY,
+ },
+ [CGT_MDCR_TPM] = {
+ .index = MDCR_EL2,
+ .value = MDCR_EL2_TPM,
+ .mask = MDCR_EL2_TPM,
+ .behaviour = BEHAVE_FORWARD_ANY,
+ },
+ [CGT_MDCR_TDE] = {
+ .index = MDCR_EL2,
+ .value = MDCR_EL2_TDE,
+ .mask = MDCR_EL2_TDE,
+ .behaviour = BEHAVE_FORWARD_ANY,
+ },
+ [CGT_MDCR_TDA] = {
+ .index = MDCR_EL2,
+ .value = MDCR_EL2_TDA,
+ .mask = MDCR_EL2_TDA,
+ .behaviour = BEHAVE_FORWARD_ANY,
+ },
+ [CGT_MDCR_TDOSA] = {
+ .index = MDCR_EL2,
+ .value = MDCR_EL2_TDOSA,
+ .mask = MDCR_EL2_TDOSA,
+ .behaviour = BEHAVE_FORWARD_ANY,
+ },
+ [CGT_MDCR_TDRA] = {
+ .index = MDCR_EL2,
+ .value = MDCR_EL2_TDRA,
+ .mask = MDCR_EL2_TDRA,
+ .behaviour = BEHAVE_FORWARD_ANY,
+ },
+ [CGT_MDCR_E2PB] = {
+ .index = MDCR_EL2,
+ .value = 0,
+ .mask = BIT(MDCR_EL2_E2PB_SHIFT),
+ .behaviour = BEHAVE_FORWARD_ANY,
+ },
+ [CGT_MDCR_TPMS] = {
+ .index = MDCR_EL2,
+ .value = MDCR_EL2_TPMS,
+ .mask = MDCR_EL2_TPMS,
+ .behaviour = BEHAVE_FORWARD_ANY,
+ },
+ [CGT_MDCR_TTRF] = {
+ .index = MDCR_EL2,
+ .value = MDCR_EL2_TTRF,
+ .mask = MDCR_EL2_TTRF,
+ .behaviour = BEHAVE_FORWARD_ANY,
+ },
+ [CGT_MDCR_E2TB] = {
+ .index = MDCR_EL2,
+ .value = 0,
+ .mask = BIT(MDCR_EL2_E2TB_SHIFT),
+ .behaviour = BEHAVE_FORWARD_ANY,
+ },
+ [CGT_MDCR_TDCC] = {
+ .index = MDCR_EL2,
+ .value = MDCR_EL2_TDCC,
+ .mask = MDCR_EL2_TDCC,
+ .behaviour = BEHAVE_FORWARD_ANY,
+ },
};
#define MCB(id, ...) \
@@ -266,6 +349,11 @@ static const enum coarse_grain_trap_id *coarse_control_combo[] = {
MCB(CGT_HCR_TPU_TICAB, CGT_HCR_TPU, CGT_HCR_TICAB),
MCB(CGT_HCR_TPU_TOCU, CGT_HCR_TPU, CGT_HCR_TOCU),
MCB(CGT_HCR_NV1_ENSCXT, CGT_HCR_NV1, CGT_HCR_ENSCXT),
+ MCB(CGT_MDCR_TPM_TPMCR, CGT_MDCR_TPM, CGT_MDCR_TPMCR),
+ MCB(CGT_MDCR_TDE_TDA, CGT_MDCR_TDE, CGT_MDCR_TDA),
+ MCB(CGT_MDCR_TDE_TDOSA, CGT_MDCR_TDE, CGT_MDCR_TDOSA),
+ MCB(CGT_MDCR_TDE_TDRA, CGT_MDCR_TDE, CGT_MDCR_TDRA),
+ MCB(CGT_MDCR_TDCC_TDE_TDA, CGT_MDCR_TDCC, CGT_MDCR_TDE_TDA),
};
typedef enum trap_behaviour (*complex_condition_check)(struct kvm_vcpu *);
@@ -565,6 +653,122 @@ static const struct encoding_to_trap_configs encoding_to_traps[] __initdata = {
SR_RANGE_TRAP(sys_reg(3, 0, 5, 4, 4),
sys_reg(3, 0, 5, 4, 6), CGT_HCR_FIEN),
SR_TRAP(SYS_SCXTNUM_EL0, CGT_HCR_ENSCXT),
+ SR_TRAP(SYS_PMCR_EL0, CGT_MDCR_TPM_TPMCR),
+ SR_TRAP(SYS_PMCNTENSET_EL0, CGT_MDCR_TPM),
+ SR_TRAP(SYS_PMCNTENCLR_EL0, CGT_MDCR_TPM),
+ SR_TRAP(SYS_PMOVSSET_EL0, CGT_MDCR_TPM),
+ SR_TRAP(SYS_PMOVSCLR_EL0, CGT_MDCR_TPM),
+ SR_TRAP(SYS_PMCEID0_EL0, CGT_MDCR_TPM),
+ SR_TRAP(SYS_PMCEID1_EL0, CGT_MDCR_TPM),
+ SR_TRAP(SYS_PMXEVTYPER_EL0, CGT_MDCR_TPM),
+ SR_TRAP(SYS_PMSWINC_EL0, CGT_MDCR_TPM),
+ SR_TRAP(SYS_PMSELR_EL0, CGT_MDCR_TPM),
+ SR_TRAP(SYS_PMXEVCNTR_EL0, CGT_MDCR_TPM),
+ SR_TRAP(SYS_PMCCNTR_EL0, CGT_MDCR_TPM),
+ SR_TRAP(SYS_PMUSERENR_EL0, CGT_MDCR_TPM),
+ SR_TRAP(SYS_PMINTENSET_EL1, CGT_MDCR_TPM),
+ SR_TRAP(SYS_PMINTENCLR_EL1, CGT_MDCR_TPM),
+ SR_TRAP(SYS_PMMIR_EL1, CGT_MDCR_TPM),
+ SR_RANGE_TRAP(SYS_PMEVCNTRn_EL0(0),
+ SYS_PMEVCNTRn_EL0(30), CGT_MDCR_TPM),
+ SR_RANGE_TRAP(SYS_PMEVTYPERn_EL0(0),
+ SYS_PMEVTYPERn_EL0(30), CGT_MDCR_TPM),
+ SR_TRAP(SYS_PMCCFILTR_EL0, CGT_MDCR_TPM),
+ SR_TRAP(SYS_MDCCSR_EL0, CGT_MDCR_TDCC_TDE_TDA),
+ SR_TRAP(SYS_MDCCINT_EL1, CGT_MDCR_TDCC_TDE_TDA),
+ SR_TRAP(SYS_OSDTRRX_EL1, CGT_MDCR_TDCC_TDE_TDA),
+ SR_TRAP(SYS_OSDTRTX_EL1, CGT_MDCR_TDCC_TDE_TDA),
+ SR_TRAP(SYS_MDSCR_EL1, CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_OSECCR_EL1, CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBVRn_EL1(0), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBVRn_EL1(1), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBVRn_EL1(2), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBVRn_EL1(3), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBVRn_EL1(4), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBVRn_EL1(5), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBVRn_EL1(6), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBVRn_EL1(7), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBVRn_EL1(8), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBVRn_EL1(9), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBVRn_EL1(10), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBVRn_EL1(11), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBVRn_EL1(12), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBVRn_EL1(13), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBVRn_EL1(14), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBVRn_EL1(15), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBCRn_EL1(0), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBCRn_EL1(1), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBCRn_EL1(2), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBCRn_EL1(3), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBCRn_EL1(4), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBCRn_EL1(5), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBCRn_EL1(6), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBCRn_EL1(7), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBCRn_EL1(8), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBCRn_EL1(9), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBCRn_EL1(10), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBCRn_EL1(11), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBCRn_EL1(12), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBCRn_EL1(13), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBCRn_EL1(14), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGBCRn_EL1(15), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWVRn_EL1(0), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWVRn_EL1(1), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWVRn_EL1(2), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWVRn_EL1(3), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWVRn_EL1(4), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWVRn_EL1(5), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWVRn_EL1(6), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWVRn_EL1(7), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWVRn_EL1(8), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWVRn_EL1(9), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWVRn_EL1(10), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWVRn_EL1(11), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWVRn_EL1(12), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWVRn_EL1(13), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWVRn_EL1(14), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWVRn_EL1(15), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWCRn_EL1(0), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWCRn_EL1(1), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWCRn_EL1(2), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWCRn_EL1(3), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWCRn_EL1(4), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWCRn_EL1(5), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWCRn_EL1(6), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWCRn_EL1(7), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWCRn_EL1(8), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWCRn_EL1(9), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWCRn_EL1(10), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWCRn_EL1(11), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWCRn_EL1(12), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWCRn_EL1(13), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGWCRn_EL1(14), CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGCLAIMSET_EL1, CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGCLAIMCLR_EL1, CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_DBGAUTHSTATUS_EL1, CGT_MDCR_TDE_TDA),
+ SR_TRAP(SYS_OSLAR_EL1, CGT_MDCR_TDE_TDOSA),
+ SR_TRAP(SYS_OSLSR_EL1, CGT_MDCR_TDE_TDOSA),
+ SR_TRAP(SYS_OSDLR_EL1, CGT_MDCR_TDE_TDOSA),
+ SR_TRAP(SYS_DBGPRCR_EL1, CGT_MDCR_TDE_TDOSA),
+ SR_TRAP(SYS_MDRAR_EL1, CGT_MDCR_TDE_TDRA),
+ SR_TRAP(SYS_PMBLIMITR_EL1, CGT_MDCR_E2PB),
+ SR_TRAP(SYS_PMBPTR_EL1, CGT_MDCR_E2PB),
+ SR_TRAP(SYS_PMBSR_EL1, CGT_MDCR_E2PB),
+ SR_TRAP(SYS_PMSCR_EL1, CGT_MDCR_TPMS),
+ SR_TRAP(SYS_PMSEVFR_EL1, CGT_MDCR_TPMS),
+ SR_TRAP(SYS_PMSFCR_EL1, CGT_MDCR_TPMS),
+ SR_TRAP(SYS_PMSICR_EL1, CGT_MDCR_TPMS),
+ SR_TRAP(SYS_PMSIDR_EL1, CGT_MDCR_TPMS),
+ SR_TRAP(SYS_PMSIRR_EL1, CGT_MDCR_TPMS),
+ SR_TRAP(SYS_PMSLATFR_EL1, CGT_MDCR_TPMS),
+ SR_TRAP(SYS_PMSNEVFR_EL1, CGT_MDCR_TPMS),
+ SR_TRAP(SYS_TRFCR_EL1, CGT_MDCR_TTRF),
+ SR_TRAP(SYS_TRBBASER_EL1, CGT_MDCR_E2TB),
+ SR_TRAP(SYS_TRBLIMITR_EL1, CGT_MDCR_E2TB),
+ SR_TRAP(SYS_TRBMAR_EL1, CGT_MDCR_E2TB),
+ SR_TRAP(SYS_TRBPTR_EL1, CGT_MDCR_E2TB),
+ SR_TRAP(SYS_TRBSR_EL1, CGT_MDCR_E2TB),
+ SR_TRAP(SYS_TRBTRG_EL1, CGT_MDCR_E2TB),
};
static DEFINE_XARRAY(sr_forward_xa);
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-05-15 17:49 UTC|newest]
Thread overview: 94+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-15 17:30 [PATCH v10 00/59] KVM: arm64: ARMv8.3/8.4 Nested Virtualization support Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 01/59] KVM: arm64: Move VTCR_EL2 into struct s2_mmu Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 02/59] arm64: Add missing Set/Way CMO encodings Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 03/59] arm64: Add missing VA " Marc Zyngier
2023-06-05 17:46 ` Eric Auger
2023-05-15 17:30 ` [PATCH v10 04/59] arm64: Add missing ERXMISCx_EL1 encodings Marc Zyngier
2023-06-05 17:47 ` Eric Auger
2023-05-15 17:30 ` [PATCH v10 05/59] arm64: Add missing DC ZVA/GVA/GZVA encodings Marc Zyngier
2023-06-05 17:47 ` Eric Auger
2023-05-15 17:30 ` [PATCH v10 06/59] arm64: Add TLBI operation encodings Marc Zyngier
2023-06-06 9:33 ` Eric Auger
2023-05-15 17:30 ` [PATCH v10 07/59] arm64: Add AT " Marc Zyngier
2023-06-14 15:08 ` Eric Auger
2023-05-15 17:30 ` [PATCH v10 08/59] KVM: arm64: Add missing HCR_EL2 trap bits Marc Zyngier
2023-06-14 15:08 ` Eric Auger
2023-05-15 17:30 ` [PATCH v10 09/59] KVM: arm64: nv: Add trap forwarding infrastructure Marc Zyngier
2023-07-13 14:29 ` Eric Auger
2023-07-14 10:53 ` Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 10/59] KVM: arm64: nv: Add trap forwarding for HCR_EL2 Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 11/59] KVM: arm64: nv: Expose FEAT_EVT to nested guests Marc Zyngier
2023-05-15 17:30 ` Marc Zyngier [this message]
2023-05-15 17:30 ` [PATCH v10 13/59] KVM: arm64: nv: Add trap forwarding for CNTHCTL_EL2 Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 14/59] KVM: arm64: nv: Add non-VHE-EL2->EL1 translation helpers Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 15/59] KVM: arm64: nv: Handle virtual EL2 registers in vcpu_read/write_sys_reg() Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 16/59] KVM: arm64: nv: Handle SPSR_EL2 specially Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 17/59] KVM: arm64: nv: Handle HCR_EL2.E2H specially Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 18/59] KVM: arm64: nv: Save/Restore vEL2 sysregs Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 19/59] KVM: arm64: nv: Trap EL1 VM register accesses in virtual EL2 Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 20/59] KVM: arm64: nv: Trap CPACR_EL1 access " Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 21/59] KVM: arm64: nv: Respect virtual HCR_EL2.TWX setting Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 22/59] KVM: arm64: nv: Respect virtual CPTR_EL2.{TFP,FPEN} settings Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 23/59] KVM: arm64: nv: Respect virtual HCR_EL2.{NV,TSC) settings Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 24/59] KVM: arm64: nv: Configure HCR_EL2 for nested virtualization Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 25/59] KVM: arm64: nv: Support multiple nested Stage-2 mmu structures Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 26/59] KVM: arm64: nv: Implement nested Stage-2 page table walk logic Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 27/59] KVM: arm64: nv: Handle shadow stage 2 page faults Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 28/59] KVM: arm64: nv: Restrict S2 RD/WR permissions to match the guest's Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 29/59] KVM: arm64: nv: Unmap/flush shadow stage 2 page tables Marc Zyngier
2023-09-14 13:10 ` Ganapatrao Kulkarni
2023-09-14 13:37 ` Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 30/59] KVM: arm64: nv: Set a handler for the system instruction traps Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 31/59] KVM: arm64: nv: Trap and emulate AT instructions from virtual EL2 Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 32/59] KVM: arm64: nv: Trap and emulate TLBI " Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 33/59] KVM: arm64: nv: Fold guest's HCR_EL2 configuration into the host's Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 34/59] KVM: arm64: nv: Hide RAS from nested guests Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 35/59] KVM: arm64: nv: Add handling of EL2-specific timer registers Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 36/59] KVM: arm64: nv: Load timer before the GIC Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 37/59] KVM: arm64: nv: Nested GICv3 Support Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 38/59] KVM: arm64: nv: Don't load the GICv4 context on entering a nested guest Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 39/59] KVM: arm64: nv: vgic: Emulate the HW bit in software Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 40/59] KVM: arm64: nv: vgic: Allow userland to set VGIC maintenance IRQ Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 41/59] KVM: arm64: nv: Implement maintenance interrupt forwarding Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 42/59] KVM: arm64: nv: Deal with broken VGIC on maintenance interrupt delivery Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 43/59] KVM: arm64: nv: Allow userspace to request KVM_ARM_VCPU_NESTED_VIRT Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 44/59] KVM: arm64: nv: Add handling of FEAT_TTL TLB invalidation Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 45/59] KVM: arm64: nv: Invalidate TLBs based on shadow S2 TTL-like information Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 46/59] KVM: arm64: nv: Tag shadow S2 entries with nested level Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 47/59] KVM: arm64: nv: Add include containing the VNCR_EL2 offsets Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 48/59] KVM: arm64: nv: Map VNCR-capable registers to a separate page Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 49/59] KVM: arm64: nv: Move nested vgic state into the sysreg file Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 50/59] KVM: arm64: Add FEAT_NV2 cpu feature Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 51/59] KVM: arm64: nv: Sync nested timer state with FEAT_NV2 Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 52/59] KVM: arm64: nv: Fold GICv3 host trapping requirements into guest setup Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 53/59] KVM: arm64: nv: Publish emulated timer interrupt state in the in-memory state Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 54/59] KVM: arm64: nv: Allocate VNCR page when required Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 55/59] KVM: arm64: nv: Enable ARMv8.4-NV support Marc Zyngier
2023-05-15 17:31 ` [PATCH v10 56/59] KVM: arm64: nv: Fast-track 'InHost' exception returns Marc Zyngier
2023-05-15 17:31 ` [PATCH v10 57/59] KVM: arm64: nv: Fast-track EL1 TLBIs for VHE guests Marc Zyngier
2023-05-15 17:31 ` [PATCH v10 58/59] KVM: arm64: nv: Use FEAT_ECV to trap access to EL0 timers Marc Zyngier
2023-05-15 17:31 ` [PATCH v10 59/59] KVM: arm64: nv: Accelerate EL0 timer read accesses when FEAT_ECV is on Marc Zyngier
2023-05-16 16:53 ` [PATCH v10 00/59] KVM: arm64: ARMv8.3/8.4 Nested Virtualization support Eric Auger
2023-05-16 18:47 ` Marc Zyngier
2023-05-16 20:28 ` Marc Zyngier
2023-05-17 8:59 ` Eric Auger
2023-05-17 14:12 ` Marc Zyngier
2023-06-06 9:33 ` Eric Auger
2023-06-06 16:30 ` Marc Zyngier
2023-06-07 16:39 ` Eric Auger
2023-06-06 17:52 ` Miguel Luis
2023-06-07 16:40 ` Eric Auger
2023-06-10 8:25 ` Miguel Luis
2023-06-05 11:28 ` Eric Auger
2023-06-06 7:30 ` Marc Zyngier
2023-06-06 9:29 ` Eric Auger
2023-06-06 16:22 ` Marc Zyngier
2023-06-07 16:30 ` Eric Auger
2023-06-28 6:45 ` Ganapatrao Kulkarni
2023-06-29 7:03 ` Marc Zyngier
2023-07-04 12:31 ` Ganapatrao Kulkarni
2023-07-07 9:46 ` Ganapatrao Kulkarni
2023-07-11 11:56 ` Ganapatrao Kulkarni
2023-07-11 12:30 ` Marc Zyngier
2023-07-10 12:56 ` Miguel Luis
2023-07-18 10:29 ` Miguel Luis
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230515173103.1017669-13-maz@kernel.org \
--to=maz@kernel.org \
--cc=alexandru.elisei@arm.com \
--cc=andre.przywara@arm.com \
--cc=chase.conklin@arm.com \
--cc=christoffer.dall@arm.com \
--cc=darren@os.amperecomputing.com \
--cc=gankulkarni@os.amperecomputing.com \
--cc=james.morse@arm.com \
--cc=jintack@cs.columbia.edu \
--cc=kvm@vger.kernel.org \
--cc=kvmarm@lists.linux.dev \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=miguel.luis@oracle.com \
--cc=oliver.upton@linux.dev \
--cc=rmk+kernel@armlinux.org.uk \
--cc=suzuki.poulose@arm.com \
--cc=yuzenghui@huawei.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).