From: Dmitry Rokosov <ddrokosov@sberdevices.ru>
To: Jerome Brunet <jbrunet@baylibre.com>
Cc: <neil.armstrong@linaro.org>,
<mturquette@baylibre.com>,<sboyd@kernel.org>,
<robh+dt@kernel.org>,<krzysztof.kozlowski+dt@linaro.org>,
<khilman@baylibre.com>,<martin.blumenstingl@googlemail.com>,
<jian.hu@amlogic.com>,<kernel@sberdevices.ru>,
<rockosov@gmail.com>,<linux-amlogic@lists.infradead.org>,
<linux-clk@vger.kernel.org>,<devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v15 0/6] add Amlogic A1 clock controller drivers
Date: Tue, 30 May 2023 19:49:33 +0300 [thread overview]
Message-ID: <20230530164933.m42ojv357atxd4gc@CAB-WSD-L081021> (raw)
In-Reply-To: <1jilc94x0d.fsf@starbuckisacylon.baylibre.com>
Jerome,
On Tue, May 30, 2023 at 06:14:01PM +0200, Jerome Brunet wrote:
> On Wed 17 May 2023 at 16:33, Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
>
> > A1 SoC has four clock controllers on the board: PLL, Peripherals, CPU,
> > and Audio. The audio clock controller is different from others, but the
> > rest are very similar from a functional and regmap point of view.
> > This patch series add support for Amlogic A1 PLL and Peripherals clock
> > drivers.
> > It blocks all A1 peripherals mainline support and a couple of patch series,
> > which were already reviewed and acked, but weren't merged due to pending
> > clock controller drivers series, e.g.
> > https://lore.kernel.org/all/20230418111612.19479-1-ddrokosov@sberdevices.ru/
> >
> > TODO: CPU and Audio clock controllers are not included in this patch
> > series, it will be sent later. The following clks from these controllers
> > are not supported for now:
> > * Audio clks - vad, mclk_vad, mclk_d, resample_a, locker_in, mclk_b,
> > pdmdclk, pdmsysclk, eqdrc, spdifin, mclk_a, audio2_toaudiotop,
> > audio2_tovad, audio2_toddr_vad, audio2_tdmin_vad, audio2_pdm,
> > audio2_ddr_arb, audio_audiolocker, audio_eqdrc, audio_resamplea,
> > audio_spdifin, audio_toddrb, audio_toddra, audio_frddrb, audio_frddra,
> > audio_tdmoutb, audio_tdmouta, audio_loopbacka, audio_tdminlb,
> > audio_tdminb, audio_tdmina, audio_ddr_arb, mclk_c
> >
> > * CPU clks: cpu_fixed_source_sel0, cpu_fixed_source_div0,
> > cpu_fixed_source_sel1, cpu_fixed_source_div1, cpu_clk
> >
> > Validation:
> > * to double check all clk flags run below helper script:
> > pushd /sys/kernel/debug/clk
> > for f in *; do
> > if [[ -f "$f/clk_flags" ]]; then
> > flags="$(cat $f/clk_flags | awk '{$1=$1};1' | sed ':a;N;$!ba;s/\n/ | /g')"
> > echo -e "$f: $flags"
> > fi
> > done
> > popd
> >
> > * to trace current clks state use '/sys/kernel/debug/clk/clk_dump' node
> > with jq post-processing:
> > $ cat /sys/kernel/debug/clk/clk_dump | jq '.' > clk_dump.json
> >
> > * to debug clk rate propagation, compile kernel with the following
> > definition:
> > $ sed -i "s/undef CLOCK_ALLOW_WRITE_DEBUGFS/define CLOCK_ALLOW_WRITE_DEBUGFS/g" drivers/clk/clk.c
> > after that, clk_rate debug node for each clock will be available for
> > write operation
> >
>
> Applied, Thx
Thank you very much!
I noticed that you have applied version 15 of the patch. If I understand
correctly, this is because CLK_SET_RATE_NO_REPARENT for all RTC children
is preferred from your perspective. I agree with this decision. However,
version 16 includes a small refactoring patch that corrects a
misstyping by changing all sys_* related dividers and gates to
read-only operations, since they are set up from BootROM. Should I
submit this patch separately at a later time?
Also could you please clarify the official process for handling these
patches? Currently, I don't see them in the linux-amlogic for-next
branches. Is there a separate repository for clock changes? I believe
the next repository is a fork of the clock framework, but unfortunately,
I cannot seem to locate it on git.kernel.org... Apologies for the
potentially simple questions...
--
Thank you,
Dmitry
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next prev parent reply other threads:[~2023-05-30 16:50 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-17 13:33 [PATCH v15 0/6] add Amlogic A1 clock controller drivers Dmitry Rokosov
2023-05-17 13:33 ` [PATCH v15 1/6] clk: meson: make pll rst bit as optional Dmitry Rokosov
2023-05-17 13:33 ` [PATCH v15 2/6] clk: meson: introduce new pll power-on sequence for A1 SoC family Dmitry Rokosov
2023-05-17 13:33 ` [PATCH v15 3/6] dt-bindings: clock: meson: add A1 PLL clock controller bindings Dmitry Rokosov
2023-05-17 13:33 ` [PATCH v15 4/6] clk: meson: a1: add Amlogic A1 PLL clock controller driver Dmitry Rokosov
2023-05-17 13:33 ` [PATCH v15 5/6] dt-bindings: clock: meson: add A1 Peripherals clock controller bindings Dmitry Rokosov
2023-05-19 21:09 ` Martin Blumenstingl
2023-05-22 13:00 ` Dmitry Rokosov
2023-05-29 20:38 ` Martin Blumenstingl
2023-05-30 8:56 ` Jerome Brunet
2023-05-30 9:34 ` Conor Dooley
2023-05-30 16:03 ` Dmitry Rokosov
2023-05-30 19:55 ` Martin Blumenstingl
2023-05-17 13:33 ` [PATCH v15 6/6] clk: meson: a1: add Amlogic A1 Peripherals clock controller driver Dmitry Rokosov
2023-05-19 21:03 ` Martin Blumenstingl
2023-05-22 13:32 ` Dmitry Rokosov
2023-05-30 8:32 ` Jerome Brunet
2023-05-30 12:06 ` Dmitry Rokosov
2023-05-30 16:14 ` [PATCH v15 0/6] add Amlogic A1 clock controller drivers Jerome Brunet
2023-05-30 16:49 ` Dmitry Rokosov [this message]
2023-05-30 17:24 ` Dmitry Rokosov
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