[PATCH 3/5] arm64: Drop support for CnP

[Marc Zyngier <maz@kernel.org>]

Using CnP in the core architecture code was always fragile (such
as the interactions with MTE), and removing this stuff feels like
a good cleanup.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/include/asm/mmu_context.h | 14 +-------------
 arch/arm64/kernel/cpufeature.c       |  7 -------
 arch/arm64/kernel/mte.c              | 12 ------------
 arch/arm64/kernel/suspend.c          |  4 ----
 arch/arm64/mm/context.c              |  7 -------
 5 files changed, 1 insertion(+), 43 deletions(-)

diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h
index 56911691bef0..2d3953d65387 100644
--- a/arch/arm64/include/asm/mmu_context.h
+++ b/arch/arm64/include/asm/mmu_context.h
@@ -139,7 +139,7 @@ static inline void cpu_install_ttbr0(phys_addr_t ttbr0, unsigned long t0sz)
 	local_flush_tlb_all();
 	__cpu_set_tcr_t0sz(t0sz);
 
-	/* avoid cpu_switch_mm() and its SW-PAN and CNP interactions */
+	/* avoid cpu_switch_mm() and its SW-PAN interactions */
 	write_sysreg(ttbr0, ttbr0_el1);
 	isb();
 }
@@ -158,18 +158,6 @@ static inline void cpu_replace_ttbr1(pgd_t *pgdp, pgd_t *idmap)
 	/* phys_to_ttbr() zeros lower 2 bits of ttbr with 52-bit PA */
 	phys_addr_t ttbr1 = phys_to_ttbr(virt_to_phys(pgdp));
 
-	if (system_supports_cnp() && !WARN_ON(pgdp != lm_alias(swapper_pg_dir))) {
-		/*
-		 * cpu_replace_ttbr1() is used when there's a boot CPU
-		 * up (i.e. cpufeature framework is not up yet) and
-		 * latter only when we enable CNP via cpufeature's
-		 * enable() callback.
-		 * Also we rely on the cpu_hwcap bit being set before
-		 * calling the enable() function.
-		 */
-		ttbr1 |= TTBR_CNP_BIT;
-	}
-
 	replace_phys = (void *)__pa_symbol(idmap_cpu_replace_ttbr1);
 
 	__cpu_install_idmap(idmap);
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index ca4e7e1fc9fa..8f86dca5ee75 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -171,8 +171,6 @@ void dump_cpu_features(void)
 		.width = 0,				\
 	}
 
-static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
-
 static bool __system_matches_cap(unsigned int n);
 
 /*
@@ -3312,11 +3310,6 @@ static int __init init_32bit_el0_mask(void)
 }
 subsys_initcall_sync(init_32bit_el0_mask);
 
-static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
-{
-	cpu_replace_ttbr1(lm_alias(swapper_pg_dir), idmap_pg_dir);
-}
-
 /*
  * We emulate only the following system register space.
  * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7]
diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c
index 7e89968bd282..e51ee92c58df 100644
--- a/arch/arm64/kernel/mte.c
+++ b/arch/arm64/kernel/mte.c
@@ -290,18 +290,6 @@ void mte_cpu_setup(void)
 {
 	u64 rgsr;
 
-	/*
-	 * CnP must be enabled only after the MAIR_EL1 register has been set
-	 * up. Inconsistent MAIR_EL1 between CPUs sharing the same TLB may
-	 * lead to the wrong memory type being used for a brief window during
-	 * CPU power-up.
-	 *
-	 * CnP is not a boot feature so MTE gets enabled before CnP, but let's
-	 * make sure that is the case.
-	 */
-	BUG_ON(read_sysreg(ttbr0_el1) & TTBR_CNP_BIT);
-	BUG_ON(read_sysreg(ttbr1_el1) & TTBR_CNP_BIT);
-
 	/* Normal Tagged memory type at the corresponding MAIR index */
 	sysreg_clear_set(mair_el1,
 			 MAIR_ATTRIDX(MAIR_ATTR_MASK, MT_NORMAL_TAGGED),
diff --git a/arch/arm64/kernel/suspend.c b/arch/arm64/kernel/suspend.c
index 0fbdf5fe64d8..af92e2d1d55f 100644
--- a/arch/arm64/kernel/suspend.c
+++ b/arch/arm64/kernel/suspend.c
@@ -53,10 +53,6 @@ void notrace __cpu_suspend_exit(void)
 	 */
 	cpu_uninstall_idmap();
 
-	/* Restore CnP bit in TTBR1_EL1 */
-	if (system_supports_cnp())
-		cpu_replace_ttbr1(lm_alias(swapper_pg_dir), idmap_pg_dir);
-
 	/*
 	 * PSTATE was not saved over suspend/resume, re-enable any detected
 	 * features that might not have been set correctly.
diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c
index e1e0dca01839..3c65644ed770 100644
--- a/arch/arm64/mm/context.c
+++ b/arch/arm64/mm/context.c
@@ -218,9 +218,6 @@ void check_and_switch_context(struct mm_struct *mm)
 	unsigned int cpu;
 	u64 asid, old_active_asid;
 
-	if (system_supports_cnp())
-		cpu_set_reserved_ttbr0();
-
 	asid = atomic64_read(&mm->context.id);
 
 	/*
@@ -352,10 +349,6 @@ void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm)
 	unsigned long asid = ASID(mm);
 	unsigned long ttbr0 = phys_to_ttbr(pgd_phys);
 
-	/* Skip CNP for the reserved ASID */
-	if (system_supports_cnp() && asid)
-		ttbr0 |= TTBR_CNP_BIT;
-
 	/* SW PAN needs a copy of the ASID in TTBR0 for entry */
 	if (IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN))
 		ttbr0 |= FIELD_PREP(TTBR_ASID_MASK, asid);
-- 
2.39.2


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