From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 26BB0C7EE23 for ; Thu, 1 Jun 2023 14:25:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=VHlf0VaA3Bjg5nkiu/ZJOETJ5u4QoMteQz9VbzkD48c=; b=YVRq0kEZzdlWJ/ 5Ce1Mygr2V6AQ+q7YLBr66zT3kynZlD5RZ6FEPgonBCoqCrYhJR2UiU9a4WO0DcliWMiDH0hQxfQZ 457kO8VxvZss5RHEW/dlOSH2f5h/in+x1RSDeQdevSWyLJSjBLV2BO50iF6B5RAjvSE57N6xTgWHL 7tXICtXJOQtOLfUs+Dtqc4OYxPWVgiet+erusvBEyYoN73I2jaeTOOASJyDQvf7YcY94Jni36ZFE3 bSC6uYhYyy1UR3sU7dexrTPRb3BbhlcFjfvGzTBQ79c1Cy5CQv0s2K/8mlowk9SI92Q8u+OLNVsG6 EzIjkUBIVD9Y1i+FW4Xw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q4jEO-003qHI-0F; Thu, 01 Jun 2023 14:24:48 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q4jEJ-003qDF-2i for linux-arm-kernel@lists.infradead.org; Thu, 01 Jun 2023 14:24:45 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 69952645C6; Thu, 1 Jun 2023 14:24:43 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C9547C433EF; Thu, 1 Jun 2023 14:24:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685629482; bh=M9wjAJWEFdK44NBUzBeqFC/bErS/Or7ne7rCGCBpJz4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=m0RE9G83mHCTNOK1csZcD/bIzrCoh6IiCs9zqlH247pDwQPRM5srR2wuIyVTEq2ek Aa4f/w1EvZLR+Uy/BFdQdew0RDwTIlztx0JUs7c4LkGPqPVvYGh9XMgvHsLUEdxbLV eNDAyDTvopC/k6b2CnVMKt6HG3R5vtKZ44tmKWV1nnI2Apj/hVPMQmbR+3A8/VWOyA 6qAxbvpSFx+t+saE5Uc5FoyItABhLN7cARCwVKAtaNQ990Z8cCgQAWGjCDOFicLn3b ZBkadLOf6mbR+NFzioeSNiJZNQOL+xJmHSvj4NUq0UBRJlqBxzsMHf2ZHzm49U7i9D WmS+D70bl8Bzw== Received: from 90.4.23.109.rev.sfr.net ([109.23.4.90] helo=localhost.localdomain) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1q4jEG-0024XU-Ik; Thu, 01 Jun 2023 15:24:40 +0100 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu Cc: Catalin Marinas , Will Deacon , Mark Rutland , Ard Biesheuvel , James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Vladimir Murzin Subject: [PATCH 3/5] arm64: Drop support for CnP Date: Thu, 1 Jun 2023 15:24:27 +0100 Message-Id: <20230601142429.12835-4-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230601142429.12835-1-maz@kernel.org> References: <20230601142429.12835-1-maz@kernel.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 109.23.4.90 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, ardb@kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, vladimir.murzin@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230601_072443_990269_E128181E X-CRM114-Status: GOOD ( 22.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Using CnP in the core architecture code was always fragile (such as the interactions with MTE), and removing this stuff feels like a good cleanup. Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/mmu_context.h | 14 +------------- arch/arm64/kernel/cpufeature.c | 7 ------- arch/arm64/kernel/mte.c | 12 ------------ arch/arm64/kernel/suspend.c | 4 ---- arch/arm64/mm/context.c | 7 ------- 5 files changed, 1 insertion(+), 43 deletions(-) diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h index 56911691bef0..2d3953d65387 100644 --- a/arch/arm64/include/asm/mmu_context.h +++ b/arch/arm64/include/asm/mmu_context.h @@ -139,7 +139,7 @@ static inline void cpu_install_ttbr0(phys_addr_t ttbr0, unsigned long t0sz) local_flush_tlb_all(); __cpu_set_tcr_t0sz(t0sz); - /* avoid cpu_switch_mm() and its SW-PAN and CNP interactions */ + /* avoid cpu_switch_mm() and its SW-PAN interactions */ write_sysreg(ttbr0, ttbr0_el1); isb(); } @@ -158,18 +158,6 @@ static inline void cpu_replace_ttbr1(pgd_t *pgdp, pgd_t *idmap) /* phys_to_ttbr() zeros lower 2 bits of ttbr with 52-bit PA */ phys_addr_t ttbr1 = phys_to_ttbr(virt_to_phys(pgdp)); - if (system_supports_cnp() && !WARN_ON(pgdp != lm_alias(swapper_pg_dir))) { - /* - * cpu_replace_ttbr1() is used when there's a boot CPU - * up (i.e. cpufeature framework is not up yet) and - * latter only when we enable CNP via cpufeature's - * enable() callback. - * Also we rely on the cpu_hwcap bit being set before - * calling the enable() function. - */ - ttbr1 |= TTBR_CNP_BIT; - } - replace_phys = (void *)__pa_symbol(idmap_cpu_replace_ttbr1); __cpu_install_idmap(idmap); diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index ca4e7e1fc9fa..8f86dca5ee75 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -171,8 +171,6 @@ void dump_cpu_features(void) .width = 0, \ } -static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); - static bool __system_matches_cap(unsigned int n); /* @@ -3312,11 +3310,6 @@ static int __init init_32bit_el0_mask(void) } subsys_initcall_sync(init_32bit_el0_mask); -static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) -{ - cpu_replace_ttbr1(lm_alias(swapper_pg_dir), idmap_pg_dir); -} - /* * We emulate only the following system register space. * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c index 7e89968bd282..e51ee92c58df 100644 --- a/arch/arm64/kernel/mte.c +++ b/arch/arm64/kernel/mte.c @@ -290,18 +290,6 @@ void mte_cpu_setup(void) { u64 rgsr; - /* - * CnP must be enabled only after the MAIR_EL1 register has been set - * up. Inconsistent MAIR_EL1 between CPUs sharing the same TLB may - * lead to the wrong memory type being used for a brief window during - * CPU power-up. - * - * CnP is not a boot feature so MTE gets enabled before CnP, but let's - * make sure that is the case. - */ - BUG_ON(read_sysreg(ttbr0_el1) & TTBR_CNP_BIT); - BUG_ON(read_sysreg(ttbr1_el1) & TTBR_CNP_BIT); - /* Normal Tagged memory type at the corresponding MAIR index */ sysreg_clear_set(mair_el1, MAIR_ATTRIDX(MAIR_ATTR_MASK, MT_NORMAL_TAGGED), diff --git a/arch/arm64/kernel/suspend.c b/arch/arm64/kernel/suspend.c index 0fbdf5fe64d8..af92e2d1d55f 100644 --- a/arch/arm64/kernel/suspend.c +++ b/arch/arm64/kernel/suspend.c @@ -53,10 +53,6 @@ void notrace __cpu_suspend_exit(void) */ cpu_uninstall_idmap(); - /* Restore CnP bit in TTBR1_EL1 */ - if (system_supports_cnp()) - cpu_replace_ttbr1(lm_alias(swapper_pg_dir), idmap_pg_dir); - /* * PSTATE was not saved over suspend/resume, re-enable any detected * features that might not have been set correctly. diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index e1e0dca01839..3c65644ed770 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -218,9 +218,6 @@ void check_and_switch_context(struct mm_struct *mm) unsigned int cpu; u64 asid, old_active_asid; - if (system_supports_cnp()) - cpu_set_reserved_ttbr0(); - asid = atomic64_read(&mm->context.id); /* @@ -352,10 +349,6 @@ void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm) unsigned long asid = ASID(mm); unsigned long ttbr0 = phys_to_ttbr(pgd_phys); - /* Skip CNP for the reserved ASID */ - if (system_supports_cnp() && asid) - ttbr0 |= TTBR_CNP_BIT; - /* SW PAN needs a copy of the ASID in TTBR0 for entry */ if (IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN)) ttbr0 |= FIELD_PREP(TTBR_ASID_MASK, asid); -- 2.39.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel