From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9DAE8C7EE24 for ; Fri, 2 Jun 2023 07:12:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=QmejafsM4en+NfTAGMQQ1AHKW6VZaMDLBf57sUSj5lQ=; b=Ynn4jkcYkATi1L le7UhCfiBpwUB2MlgtnjI1ghXjkiQnbD6FWIIWQbaigXwbo/4Ev0VEHfIThkWQ8UhXefcDswUJ/gD ZDc4TsrzGOuHLCl5FtIkEmI98VUgpmEF1yYt1FzMZ39wAlpJmGPYnQMk4aeJagMlwyINSI4UFdEIJ TR/6ngf+2t3T+onyQPNHdDneACvGrt2U34fFbNvtfrZ77lihqhHN7yRFLcZ2j3QltfiYQrIIBDx+f c8uPs4LJZqXSmeeFrtZ2m9eh1GCye5jAW4LW/rgzbSdK8f//EIFbnY2tl6tI5YVnsC7DXbKaaIdmv TnrcJlb/BGh4DFIipzbA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q4ywq-005ymd-2g; Fri, 02 Jun 2023 07:11:44 +0000 Received: from muru.com ([72.249.23.125]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q4ywo-005ylx-1E for linux-arm-kernel@lists.infradead.org; Fri, 02 Jun 2023 07:11:43 +0000 Received: from localhost (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id C62558111; Fri, 2 Jun 2023 07:11:41 +0000 (UTC) Date: Fri, 2 Jun 2023 10:11:40 +0300 From: Tony Lindgren To: Udit Kumar Cc: nm@ti.com, vigneshr@ti.com, kristo@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, conor+dt@kernel.org, m-chawdhry@ti.com, n-francis@ti.com Subject: Re: [PATCH v2 2/5] arm64: dts: ti: k3-j7200: Configure pinctrl for timer IO pads Message-ID: <20230602071140.GN14287@atomide.com> References: <20230601093744.1565802-1-u-kumar1@ti.com> <20230601093744.1565802-3-u-kumar1@ti.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230601093744.1565802-3-u-kumar1@ti.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230602_001142_462079_95A7B523 X-CRM114-Status: GOOD ( 14.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org * Udit Kumar [230601 09:38]: > There are timer IO pads in the MCU domain, and in the MAIN domain. These > pads can be muxed for the related timers. > > There are timer IO control registers for input and output. The registers > for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control > the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and > CTRLMMR_MCU_TIMERIO*_CTRL the output. > > The multiplexing is documented in TRM "5.1.2.3.1.4 Timer IO Muxing Control > Registers" and "5.1.3.3.1.5 Timer IO Muxing Control Registers", and the > CASCADE_EN bit is documented in TRM "12.6.3.1 Timers Overview". > > For chaining timers, the timer IO control registers also have a CASCADE_EN > input bit in the CTRLMMR_TIMER*_CTRL in the registers. The CASCADE_EN bit > muxes the previous timer output, or possibly and external TIMER_IO pad > source, to the input clock of the selected timer instance for odd numered > timers. For the even numbered timers, the CASCADE_EN bit does not do > anything. The timer cascade input routing options are shown in TRM > "Figure 12-3224. Timers Overview". For handling beyond multiplexing, the > driver support for timer cascading should be likely be handled via the > clock framework. > > The MCU timer controls are also marked as reserved for > usage by the MCU firmware. Reviewed-by: Tony Lindgren _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel